-
1.发明申请公开(公告)号：US20100001709A1
公开(公告)日：2010-01-07
申请号：US12168133
申请日：2008-07-06
IPC分类号： G05F3/18
摘要： A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor.
摘要翻译： 产生电荷泵的参考的系统可以包括提供参考电压的二极管连接的晶体管和输出晶体管。 该系统还可以包括用于提供基本上温度不敏感的电流的参考电路，并且该参考电路传送跨过二极管连接的晶体管的电流，从而使得参考电压随二极管连接的晶体管的处理而移动。
-
公开(公告)号：US20100001696A1
公开(公告)日：2010-01-07
申请号：US12166192
申请日：2008-07-01
CPC分类号： H02M3/07
摘要： A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.
摘要翻译： 改进多级电荷泵的系统可以包括电容器，由电容器承载的第一板以及由电容器与第一板相对的第二板。 该系统还可以包括用于控制电容器的充电和放电的时钟。 该系统还可以包括电源，以在电容器充电期间在第一板和第二板两端提供电源电压。 该系统还可以包括用于在电容器放电期间将第二板提升到中间电压的电压线。 该系统还可以包括在电容器放电期间连接到第一板以提供输出电压的输出线。
-
公开(公告)号：US08258758B2
公开(公告)日：2012-09-04
申请号：US12166192
申请日：2008-07-01
IPC分类号： H02J7/00
CPC分类号： H02M3/07
摘要： A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.
摘要翻译： 改进多级电荷泵的系统可以包括电容器，由电容器承载的第一板以及由电容器与第一板相对的第二板。 该系统还可以包括用于控制电容器的充电和放电的时钟。 该系统还可以包括电源，以在电容器充电期间在第一板和第二板两端提供电源电压。 该系统还可以包括用于在电容器放电期间将第二板提升到中间电压的电压线。 该系统还可以包括在电容器放电期间连接到第一板以提供输出电压的输出线。
-
公开(公告)号：US20100002478A1
公开(公告)日：2010-01-07
申请号：US12166433
申请日：2008-07-02
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： A system to improve a voltage multiplier may include a voltage multiplier circuit, and a capacitor carried by the multiplier circuit. The system may also include a transistor to charge an up voltage of the capacitor.
摘要翻译： 改善电压倍增器的系统可以包括电压倍增器电路和乘法器电路承载的电容器。 该系统还可以包括用于对电容器的上升电压充电的晶体管。
-
5.发明申请SENSE AMPLIFIER HAVING AN ISOLATED PRE-CHARGE ARCHITECTURE, A MEMORY CIRCUIT INCORPORATING SUCH A SENSE AMPLIFIER AND ASSOCIATED METHODS 失效具有隔离预充电结构的感测放大器，包含这种感测放大器的记忆电路及相关方法公开(公告)号：US20130114361A1
公开(公告)日：2013-05-09
申请号：US13288424
申请日：2011-11-03
CPC分类号： G11C7/065 , G11C11/4091
摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.
摘要翻译： 公开了一种读出放大器和包含它的存储器电路。 放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。 一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。 在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。 开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。 在这种情况下，感测节点放电到与输入信号相同的电平。 否则，交换机可防止电气连接，并且感测节点保持高电平。 跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。 还公开了相关联的方法。
-
6.发明授权Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods 失效具有隔离预充电架构的感测放大器，结合了这种读出放大器的存储电路和相关联的方法公开(公告)号：US08605528B2
公开(公告)日：2013-12-10
申请号：US13288424
申请日：2011-11-03
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091
摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.
摘要翻译： 公开了一种读出放大器和包含它的存储器电路。 放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。 一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。 在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。 开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。 在这种情况下，感测节点放电到与输入信号相同的电平。 否则，交换机可防止电气连接，并且感测节点保持高电平。 跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。 还公开了相关联的方法。
-
公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
-
公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
-
9.发明申请WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS 失效用于配置多个存储器子选项的存储器阵列的写控制方法公开(公告)号：US20080247245A1
公开(公告)日：2008-10-09
申请号：US12139675
申请日：2008-06-16
IPC分类号： G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。
-
公开(公告)号：US07403412B2
公开(公告)日：2008-07-22
申请号：US11782282
申请日：2007-07-24
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。
-
-
-
-
-
-
-
-
-
搜索结果
52 条记录 (耗时 0.039 秒)
