公开(公告)号：US20130114361A1

公开(公告)日：2013-05-09

申请号：US13288424

申请日：2011-11-03

申请人： John E. Barth, JR. ,  Donald W. Plass ,  Adis Vehabovic

发明人： John E. Barth, JR. ,  Donald W. Plass ,  Adis Vehabovic

IPC分类号： G11C7/06 ,  H03F3/16

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.

摘要翻译： 公开了一种读出放大器和包含它的存储器电路。 放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。 一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。 在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。 开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。 在这种情况下，感测节点放电到与输入信号相同的电平。 否则，交换机可防止电气连接，并且感测节点保持高电平。 跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。 还公开了相关联的方法。

公开(公告)号：US20100001709A1

公开(公告)日：2010-01-07

申请号：US12168133

申请日：2008-07-06

申请人： John E. Barth, JR. ,  Charlie C. Hwang ,  Paul D. Muench ,  Donald W. Plass ,  Michael Sperling

发明人： John E. Barth, JR. ,  Charlie C. Hwang ,  Paul D. Muench ,  Donald W. Plass ,  Michael Sperling

IPC分类号： G05F3/18

CPC分类号： G05F3/16 ,  G11C5/145

摘要： A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor.

摘要翻译： 产生电荷泵的参考的系统可以包括提供参考电压的二极管连接的晶体管和输出晶体管。 该系统还可以包括用于提供基本上温度不敏感的电流的参考电路，并且该参考电路传送跨过二极管连接的晶体管的电流，从而使得参考电压随二极管连接的晶体管的处理而移动。

公开(公告)号：US20130262792A1

公开(公告)日：2013-10-03

申请号：US13431108

申请日：2012-03-27

申请人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

发明人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

IPC分类号： G06F12/00

CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.

摘要翻译： 实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数 在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。 该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控​​制器处接收频率改变请求，频率改变请求以新频率操作并更新第一 模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

公开(公告)号：US20110267916A1

公开(公告)日：2011-11-03

申请号：US12770976

申请日：2010-04-30

申请人： John E. Barth, JR.

发明人： John E. Barth, JR.

IPC分类号： G11C5/14

CPC分类号： G11C11/4091

摘要： A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.

摘要翻译： 直接读出存储器阵列结构和操作方法包括多个存储器单元，其中位线恢复电压电平被优化以在第一非活动时段期间减少存储器单元泄漏，并且位线预设电压电平被优化用于信号感测 在第二个活跃期间。 该架构包括具有一对交叉耦合门控反相器的感测头。 每个门控逆变器响应于第一和第二门控制信号，该第一和第二门控制信号可以独立地对每个门控逆变器内的逆变器电路的电源供电。 在第二活动期间，第一选通逆变器检测第一位线上的数据状态，第二门控反相器在第一位线上执行预置和回写功能。

公开(公告)号：US20110177659A1

公开(公告)日：2011-07-21

申请号：US13075552

申请日：2011-03-30

申请人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

发明人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

IPC分类号： H01L21/336

CPC分类号： H01L29/78615

摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.

摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。 体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

公开(公告)号：US20100001788A1

公开(公告)日：2010-01-07

申请号：US12168136

申请日：2008-07-06

申请人： John E. Barth, JR. ,  John A. Fifield ,  Fadi H. Gebara ,  Jente B. Kuang ,  Michael Sperling

发明人： John E. Barth, JR. ,  John A. Fifield ,  Fadi H. Gebara ,  Jente B. Kuang ,  Michael Sperling

IPC分类号： G05F3/02 ,  G05F1/10

CPC分类号： H02M3/07

摘要： A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.

摘要翻译： 用于评估电荷泵输出的系统可以包括比较器，用于将电荷泵输出电压与参考电压进行比较以产生比较结果。 该系统还可以包括用于分频时钟信号的分频器。 该系统还可以包括对比较结果和划分的下降时钟信号进行操作的逻辑连接单元。

公开(公告)号：US20130285193A1

公开(公告)日：2013-10-31

申请号：US13457601

申请日：2012-04-27

申请人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

发明人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

公开(公告)号：US20100157698A1

公开(公告)日：2010-06-24

申请号：US12343554

申请日：2008-12-24

申请人： John E. Barth, JR.

发明人： John E. Barth, JR.

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C11/4091

摘要： According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.

摘要翻译： 根据本发明的实施例，用于例如DRAM数据存储单元的阵列的读出放大器包括串联连接在一起的一个或多个放大器级。 放大器级一起形成用于DRAM阵列的读出放大器。 每个放大器级包括隔离电容器，以将每个放大器级内的晶体管的阈值电压之间的失配降至相对较小的值。 存储器单元的DRAM阵列的位线连接到第一放大器级。 来自最后一个放大器级的输出端连接到写回开关，其回输开关在第一放大器级的输入处连接到位线。

公开(公告)号：US20090224304A1

公开(公告)日：2009-09-10

申请号：US12045190

申请日：2008-03-10

申请人： Ethan H. Cannon ,  John E. Barth, JR. ,  Kerry Bernstein

发明人： Ethan H. Cannon ,  John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L27/105 ,  H01L21/8232

CPC分类号： H01L29/66181 ,  G11C5/005 ,  H01L21/765 ,  H01L27/0629 ,  H01L27/11 ,  H01L29/945

摘要： A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.

摘要翻译： 在具有第一导电类型的掺杂的半导体层中形成包含掺杂半导体填充部分的深沟槽，该掺杂半导体填充部分具有第一导电类型掺杂并被由下部具有第二导电类型掺杂的掩埋板包围。 形成与掩埋板层相邻的第二导电类型的掺杂阱。 掺杂半导体填充部分用作由辐射颗粒产生的第一导电类型的电荷的临时储存器，并且掩埋板层用作第二导电类型的电荷的临时储存器。 掩埋板层和掺杂半导体填充部分形成电容器，并且提供对软错误的保护以防止在半导体层或掺杂阱中形成的器件。

公开(公告)号：US20090144506A1

公开(公告)日：2009-06-04

申请号：US11949904

申请日：2007-12-04

申请人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, JR. ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  Y02D10/13

摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一： 高速缓存行的使用历史。 对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分 。