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公开(公告)号：US06759282B2
公开(公告)日：2004-07-06
申请号：US09879530
申请日：2001-06-12
IPC分类号： H01L2100
CPC分类号： H01L29/78648 , H01L21/743 , H01L21/76251 , H01L21/84 , H01L27/10832 , H01L27/10873 , H01L27/11803 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.
摘要翻译： 一种使用导致形成掩埋氧化物层的SOI技术制造电子器件的方法和结构。 该方法包括制造电子器件的至少一个第一部件并且制造电子器件的至少一个第二部件，其中第一部件和第二部件在掩埋氧化物层的相对侧上，从而使掩埋氧化物层 执行电子设备内的功能。 可以围绕这种技术设计整个电路。
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公开(公告)号：US07491588B2
公开(公告)日：2009-02-17
申请号：US11598507
申请日：2006-11-13
CPC分类号： H01L29/78648 , H01L21/743 , H01L21/76251 , H01L21/84 , H01L27/10832 , H01L27/10873 , H01L27/11803 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. The first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.
摘要翻译： 提供了一种用于在绝缘体上半导体（SOI）衬底上制造互补金属氧化物半导体（CMOS）电路的方法。 形成多个场效应晶体管（FET），每个具有设置在SOI衬底的单晶半导体层内的公共器件层中的沟道区。 第一FET的栅极覆盖在公共器件层的上表面，第二FET的栅极位于远离上表面的公共器件层的下表面。 第一和第二FET共享设置在公共器件层中的公共扩散区域，并通过公共扩散区域导电互连。 公共扩散区域可操作为第一FET的源极区域或漏极区域中的至少一个，并且可以同时工作为第二FET的源极区域或漏极区域中的至少一个。
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公开(公告)号：US07141853B2
公开(公告)日：2006-11-28
申请号：US10832894
申请日：2004-04-27
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/743 , H01L21/76251 , H01L21/84 , H01L27/10832 , H01L27/10873 , H01L27/11803 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device.Entire circuits can be designed around this technique.
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公开(公告)号：US07320918B2
公开(公告)日：2008-01-22
申请号：US11126675
申请日：2005-05-11
IPC分类号： H01L21/336
CPC分类号： H01L29/78648 , H01L21/743 , H01L21/76251 , H01L21/84 , H01L27/10832 , H01L27/10873 , H01L27/11803 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.
摘要翻译： 一种使用导致形成掩埋氧化物层的SOI技术制造电子器件的方法和结构。 该方法包括制造电子器件的至少一个第一部件并且制造电子器件的至少一个第二部件，其中第一部件和第二部件在掩埋氧化物层的相对侧上，从而使掩埋氧化物层 执行电子设备内的功能。 可以围绕这种技术设计整个电路。
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5.发明授权Dynamic object-level code translation for improved performance of a computer processor 失效动态对象级代码转换，以改善计算机处理器的性能公开(公告)号：US08200987B2
公开(公告)日：2012-06-12
申请号：US12197613
申请日：2008-08-25
IPC分类号： G06F11/30
CPC分类号： G06F9/30174 , G06F9/3017
摘要： A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.
摘要翻译： 一种用于提高计算机处理器中的对象级指令流的效率的系统和方法。 用于在RISC架构的计算机处理器中从对象级指令流生成翻译指令的翻译逻辑和执行翻译指令的执行单元集成到处理器中。 翻译逻辑将多个对象级指令的功能组合成单个转换的指令，该指令与非翻译指令相比可以被分派到单个执行单元，否则将被顺序地分派到单独的执行单元。 因此，可以扩展处理器的吞吐量，因为每个周期可以调度的指令的数量被扩展。
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6.发明申请DYNAMIC OBJECT-LEVEL CODE TRANSLATION FOR IMPROVED PERFORMANCE OF A COMPUTER PROCESSOR 失效用于改进计算机处理器性能的动态对象级代码转换公开(公告)号：US20080320286A1
公开(公告)日：2008-12-25
申请号：US12197613
申请日：2008-08-25
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/3017
摘要： A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.
摘要翻译： 一种用于提高计算机处理器中的对象级指令流的效率的系统和方法。 用于在RISC架构的计算机处理器中从对象级指令流生成翻译指令的翻译逻辑和执行翻译指令的执行单元集成到处理器中。 翻译逻辑将多个对象级指令的功能组合成单个转换的指令，该指令与非翻译指令相比可以被分派到单个执行单元，否则将被顺序地分派到单独的执行单元。 因此，可以扩展处理器的吞吐量，因为每个周期可以调度的指令的数量被扩展。
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7.发明授权公开(公告)号：US07418580B1
公开(公告)日：2008-08-26
申请号：US09452955
申请日：1999-12-02
CPC分类号： G06F9/30174 , G06F9/3017
摘要： A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.
摘要翻译： 一种用于提高计算机处理器中的对象级指令流的效率的系统和方法。 用于在RISC架构的计算机处理器中从对象级指令流生成翻译指令的翻译逻辑和执行翻译指令的执行单元集成到处理器中。 翻译逻辑将多个对象级指令的功能组合成单个转换的指令，该指令与非翻译指令相比可以被分派到单个执行单元，否则将被顺序地分派到单独的执行单元。 因此，可以扩展处理器的吞吐量，因为每个周期可以调度的指令的数量被扩展。
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8.发明授权CMOS driver circuit for providing a logic function while reducing pass-through current 失效CMOS驱动电路，用于提供逻辑功能，同时减少通过电流
公开(公告)号：US6025739A
公开(公告)日：2000-02-15
申请号：US63065
申请日：1998-04-21
IPC分类号： H03K19/00 , H03K19/096 , H03K17/16 , H03K19/094 , H03K19/20
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A CMOS driver circuit minimizes a pass-through current flowing from a first voltage terminal to a second voltage terminal during transitions of an input signal. At least two transistors are connected in series between two voltage terminals. One transistor turns off when the input signal transitions from a low logic state to a high logic state. Another transistor turns off when the input signal transitions high-to-low. During either input signal transition, one of the transistors is off, thereby cutting the path between the voltage terminals to reduce or eliminate the pass-through current. The two transistors are controlled by the output of the circuit through a feedback loop. This feedback loop can include a delay element, one transistor controlled by a single synchronizing clock signal, or two transistors controlled by two complementary clock signals. The driver circuit can be used as a building block to provide conventional combination logic functions. Specific embodiments for an inverter and a NOR gate are described.
摘要翻译： 在输入信号的转变期间，CMOS驱动电路最小化从第一电压端子流向第二电压端子的通过电流。 至少两个晶体管串联在两个电压端子之间。 当输入信号从低逻辑状态转换到高逻辑状态时，一个晶体管截止。 当输入信号从高电平变为低电平时，另一个晶体管截止。 在任一输入信号转换期间，一个晶体管截止，从而切断电压端之间的路径，以减少或消除直通电流。 两个晶体管由电路的输出通过反馈回路控制。 该反馈环路可以包括延迟元件，由单个同步时钟信号控制的一个晶体管或由两个互补时钟信号控制的两个晶体管。 驱动器电路可以用作构建块以提供常规的组合逻辑功能。 描述了逆变器和或非门的具体实施例。
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公开(公告)号：US09228406B2
公开(公告)日：2016-01-05
申请号：US13563378
申请日：2012-07-31
摘要： A cutting apparatus and method to facilitate milling of a casing window by improving the interaction between the mill and the casing. The cutting apparatus comprises a whipstock having a plurality of ramp sections which provide a ramp profile arranged and designed to cooperate with the cutting structure of a mill to achieve a desired loading on the mill cutting elements during milling of the casing window. The plurality of ramp sections, having specific lengths and oriented at specific angles, adjust the loading on the mill as the mill cuts through the casing during formation of the casing window. The improved whipstock maintains a more balanced loading across the cutting elements during milling operations. Additional mill cutting structures may also be selected and evaluated to further balance the cutting load during window milling.
摘要翻译： 一种切削装置和方法，用于通过改善轧机和套管之间的相互作用来促进套管窗的铣削。 切割装置包括具有多个斜面部分的造斜器，该斜面部分提供了斜面轮廓，该坡道轮廓布置和设计成与铣刀的切割结构配合，以在铣削窗口的铣削期间实现对切割元件的期望载荷。 具有特定长度并且以特定角度定向的多个斜坡部分在机壳窗口形成期间随着铣刀穿过壳体而调节磨机上的负载。 改进的造斜器在铣削操作期间在切割元件上保持更平衡的负载。 还可以选择和评估另外的铣削切割结构，以进一步平衡窗铣过程中的切削负载。
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公开(公告)号：US08967300B2
公开(公告)日：2015-03-03
申请号：US13345400
申请日：2012-01-06
申请人： Charles H Dewey , John E. Campbell , Daniel LeVon
发明人： Charles H Dewey , John E. Campbell , Daniel LeVon
IPC分类号： E21B10/32
CPC分类号： E21B10/322 , E21B21/103 , E21B34/10 , E21B2034/007
摘要： A downhole tool includes a pressure activated flow switch for selectively actuating and deactuating a device, such as a reaming block. The flow switch is deployed external to the flow bore and includes a flow piston configured to reciprocate between axially opposed open and closed positions such that the device is actuated when the flow piston is in the open position and deactuated when the flow piston is in the closed position. The flow piston is configured to translate from the closed position to the open position when a differential pressure exceeds a predetermined threshold. The flow piston may be further configured to remain in the open position at differential pressures less than the threshold.
摘要翻译： 井下工具包括用于选择性地致动和停用诸如铰孔块的装置的压力启动流量开关。 流动开关被布置在流动孔的外部，并且包括流动活塞，流动活塞构造成在轴向相对的打开和关闭位置之间往复运动，使得当流动活塞处于打开位置时该装置被致动，并且当流动活塞处于关闭状态时停止运动 位置。 流动活塞构造成当压差超过预定阈值时从关闭位置平移到打开位置。 流动活塞可进一步构造成在小于阈值的差压下保持打开位置。
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