公开(公告)号：US4615016A

公开(公告)日：1986-09-30

申请号：US537910

申请日：1983-09-30

申请人： John J. Bradley ,  Brian L. Stoffers ,  Theodore R. Staplin, Jr. ,  Melinda A. Widen

发明人： John J. Bradley ,  Brian L. Stoffers ,  Theodore R. Staplin, Jr. ,  Melinda A. Widen

IPC分类号： G06F7/491 ,  G06F7/52

CPC分类号： G06F7/4915

摘要： Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.

摘要翻译： 描述了用于执行二进制和十进制算术运算的处理器装置。 在与处理器装置执行十进制相乘时，为了减少要用设备进行的处理量，从而加速小数乘法的执行，识别在乘法器和被乘数中的最高有效数字前面的前导零被识别 ，计数和删除。 然后使用剥离的乘法器和被乘数器执行十进制乘法，并且对于所得到的部分乘积，零数量被设为等于从乘法器和被乘数最初剥离的零数。 结果是原始乘法器和被乘数的乘积。

公开(公告)号：US4608659A

公开(公告)日：1986-08-26

申请号：US537991

申请日：1983-09-30

申请人： John J. Bradley ,  Theodore R. Staplin, Jr. ,  Ming T. Miu ,  Thomas C. O'Brien ,  George M. O'Har ,  Melinda A. Widen ,  Brian L. Stoffers

发明人： John J. Bradley ,  Theodore R. Staplin, Jr. ,  Ming T. Miu ,  Thomas C. O'Brien ,  George M. O'Har ,  Melinda A. Widen ,  Brian L. Stoffers

IPC分类号： G06F7/48 ,  G06F7/57 ,  G06F11/10

CPC分类号： G06F7/57 ,  G06F7/491 ,  G06F7/49905

摘要： What is disclosed is apparatus making up an arithmetic logic unit and utilizing a programmable read-only memory (PROM) to perform arithmetic functions for an associated processor. The PROM is used as a look-up table for computation results. Operands used to perform a mathematical computation make up an address to the PROM which is used to read out the computation result stored therein. Also stored in the PROM as part of each computation result are information bits indicating if the computation result is a valid answer. These bits are also read out and stored in flip-flops to indicate to the processor if the computation result is valid or invalid.

摘要翻译： 所公开的是组成算术逻辑单元并利用可编程只读存储器（PROM）来执行相关处理器的算术功能的装置。 PROM用作计算结果的查找表。 用于执行数学计算的操作数构成了用于读出存储在其中的计算结果的PROM的地址。 作为每个计算结果的一部分，还存储在PROM中的是指示计算结果是否是有效答案的信息比特。 这些位也被读出并存储在触发器中以向处理器指示计算结果是有效还是无效。

公开(公告)号：US4604722A

公开(公告)日：1986-08-05

申请号：US537899

申请日：1983-09-30

申请人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Brian L. Stoffers

发明人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Brian L. Stoffers

IPC分类号： G06F7/48 ,  G06F7/491

CPC分类号： G06F7/491

摘要： A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.

摘要翻译： 描述了具有能够执行二进制和十进制算术软件指令的中央处理单元（CPU）的数据处理系统。 CPU包括在固件控制下执行二进制算术软件指令的微处理器。 还公开了与CPU一起使用的算术逻辑单元（ALU）。 ALU具有操作数输入，连接的切换导向电路允许特定操作数和零操作数选择性地施加到ALU操作数输入中的任何一个或全部。 这允许简单的执行特殊的算术运算功能，例如在将十进制操作数转换为二进制操作数时将其自身加一个十进制操作数，并在补零十进制操作数时从零中减去十进制操作数。

公开(公告)号：US4321665A

公开(公告)日：1982-03-23

申请号：US8121

申请日：1979-01-31

申请人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

发明人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/40 ,  G06F3/00

CPC分类号： G06F13/4013

摘要： In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

摘要翻译： 在包括中央处理单元（CPU）的数据处理系统中，主存储器和连接到公共总线信息的多个输入/输出控制器（IOC）可以在主存储器和CPU以及主存储器和IOC之间传送。 在CPU内部提供逻辑，以便在公共总线的数据线上对齐一个数据字节，使得它可以从主存储器从数据线中取出，并写入多字节字而无需进一步对齐。 在CPU中提供逻辑以从从主存储器读取的数据的多字节字提取出公共总线数据线上相应的数据字节并将其对准在公共总线数据线上，使得IOC可以传递数据 字节到外围设备，无需进一步对齐。

公开(公告)号：US4293908A

公开(公告)日：1981-10-06

申请号：US8001

申请日：1979-01-31

申请人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理单元（CPU）。 提供逻辑用于在直接存储器访问（DMA）数据传输操作期间传送一个数据单元，其中请求IOC请求CPU的DMA数据传输。 在系统内提供的装置是：解决对一个或多个公共总线的冲突请求，CPU确认DMA请求，IOC将要写入数据单元的位置的地址传送到主存储器，之后是 数据单元或IOC传输要从其读取数据单元的主存储器中的位置的地址，然后接收从主存储器读取的数据单元。

公开(公告)号：US4383295A

公开(公告)日：1983-05-10

申请号：US11001

申请日：1979-02-09

申请人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F3/02 ,  G06F9/06

CPC分类号： G06F3/0227

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 为了允许数据输入操作者通过连接到IOC的外围设备输入数据以校正错误的能力，提供退格字符，以便操作者可以进入它以指示系统忽略前一个字符。 在系统中提供逻辑，以允许DMC IOC从连接到IOC的外围设备检测退格字符的输出，并通过特殊（退格）输入/输出中断向CPU通知退格字符的输入。 在CPU内提供进一步的逻辑来调整指向主存储器输入缓冲器的指针，以有效地忽略与退格字符之前的字符相对应的数据字节。 在DMC IOC中还提供了一些逻辑，以禁止在CPU中输入/输出特殊的（空格）输入/输出中断，如果输入缓冲区中没有字节数据。

公开(公告)号：US4300193A

公开(公告)日：1981-11-10

申请号：US8003

申请日：1979-01-31

申请人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F3/00

CPC分类号： G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到多个输入/输出控制器用于信息的传送，信息块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 逻辑被提供用于使得在数据复用控制（DMC）数据传送操作期间传送信息块的一个单元，其中请求的IOC请求CPU的DMC数据传送，并向CPU提供分配给 请求IOC。 在CPU内提供用于确定：数据传送的方向，要传送到主存储器的数据单元的位置的地址以及在主存储器之间传输的剩余数据的单元数量 记忆和国际奥委会。

公开(公告)号：US4495571A

公开(公告)日：1985-01-22

申请号：US339278

申请日：1982-01-15

申请人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

发明人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F3/04 ,  G06F13/00

CPC分类号： G06F13/122 ,  G06F13/362

摘要： A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

摘要翻译： 包括通过公共总线与多个输入/输出控制器（IOC）和主存储器耦合的中央处理单元的数据处理系统包括允许IOC发信号通知CPU等待并重试当前I / O指令的装置。 提供了其他设备，使得CPU能够连续地重试I / O指令，直到IOC接受或拒绝I / O指令，并且还允许CPU暂停重试I / O指令并处理中断请求和数据 转移来自多个IOC中的任何一个的请求。 处理中断或数据传输请求后，返回系统控制以重试I / O指令。

公开(公告)号：US4292668A

公开(公告)日：1981-09-29

申请号：US8002

申请日：1979-01-31

申请人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F3/00

CPC分类号： G06F13/362 ,  G06F13/285

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 在系统内提供了：解决对一个或多个公共总线的冲突请求，CPU确认DMC请求，识别请求的IOC到CPU，从主存储器或IOC访问一个单元的数据，并传送 数据单位到IOC或主存储器。

公开(公告)号：US4727486A

公开(公告)日：1988-02-23

申请号：US858786

申请日：1986-05-02

申请人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

发明人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

IPC分类号： G06F12/10 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30

CPC分类号： G06F12/1054

摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.