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公开(公告)号：US5379280A
公开(公告)日：1995-01-03
申请号：US766649
申请日：1991-09-26
申请人： John M. Cotton , Neil C. Olsen , Alex T. Wissink , Gary V. Pieper , William A. Oswald , Nicholas Necula , Enrique Abreu , Maurice J. Mascarenhas , Rudy De Bruyn
发明人： John M. Cotton , Neil C. Olsen , Alex T. Wissink , Gary V. Pieper , William A. Oswald , Nicholas Necula , Enrique Abreu , Maurice J. Mascarenhas , Rudy De Bruyn
CPC分类号： H04M3/562 , H04M3/561 , H04Q11/0478 , H04L2012/5642 , H04L2012/5643 , H04M9/008
摘要： A conferencing device and method among terminals in a distributed digital telephone switching system is provided. The telephone switching system has a plurality of switching elements for interconnecting telephone units and telephone lines via communication links. A duplex path is set between each party in the conference and a designated bridge port. The speech from all the parties in the conference is summed and at the bridge port the sum is sent back to all engaged in the conference. As each party receives the sum, it subtracts its own speech data and therefore obtains the speech data from the other parties in the conference.
摘要翻译： 提供了分布式数字电话交换系统中的终端之间的会议设备和方法。 电话交换系统具有用于经由通信链路互连电话单元和电话线路的多个开关元件。 在会议中的每一方和指定的桥接端口之间设置双工路径。 会议中所有各方的讲话总结，在桥港口将总额送回所有参加会议的人员。 当各方收到总和时，减去自己的语音数据，从而在会议中从其他各方获取语音数据。
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2.发明授权
公开(公告)号：US5255264A
公开(公告)日：1993-10-19
申请号：US766047
申请日：1991-09-26
申请人： John M. Cotton , Neil C. Olsen , Alex T. Wissink , Gary V. Pieper , William A. Oswald , Nicholas Necula , Enrique Abreu , Maurice J. Mascarenhas , Rudy De Bruyn
发明人： John M. Cotton , Neil C. Olsen , Alex T. Wissink , Gary V. Pieper , William A. Oswald , Nicholas Necula , Enrique Abreu , Maurice J. Mascarenhas , Rudy De Bruyn
CPC分类号： H04Q11/0407 , H04M3/561 , H04Q2213/13103 , H04Q2213/13107 , H04Q2213/13144 , H04Q2213/13174
摘要： A communication switching system with distributed control processing is provided. The system includes a digital switching network having a modular array of intelligent digital switching elements each having processors and memory to set up communication paths for voice and data between the terminal module processors such as line cards and telephone units. Each addressable location in the system is assigned a logical address code (LAC). When a route is requested, a switch element processor interprets the destination LAC and selects a route through the switch toward the destination with each switch element in the communication path setting a route toward that destination. The switching network provides duplex paths for flexible communication. With such a duplex path speech is directed from a first terminal unit such as a telephone station and a second terminal unit such as a line card into a bridge port which sums the speech data from the two sources. The summed speech is then sent from the bridge port to the terminal units.
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公开(公告)号：US5870441A
公开(公告)日：1999-02-09
申请号：US918006
申请日：1997-08-25
申请人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
发明人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
CPC分类号： H04J3/0688 , G06F1/04 , G06F1/08 , H04J3/0691 , H04L7/0337
摘要： A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.
摘要翻译： 具有改进的用于同步分布式处理系统的容错性的计时机构包括多个分布式时钟源。 每个时钟源可以用作主时钟，用于将整个系统的操作或作为从设备的操作同步到外部时钟，同时在备用容量中保持可用，在前一个主站发生故障的情况下作为主时钟操作 时钟。 在每个分布式开关元件中提供时钟选择机制，用于选择可用于每个开关元件以用于同步的最佳时钟。 在主时钟故障的情况下，故障恢复机制提供快速和自动的恢复。 即使存在定时抖动和脉冲宽度失真，也提供了能够采样不相位对准的位流的数据提取机构，并且具有用于检测位滑动的规定。
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公开(公告)号：US5577075A
公开(公告)日：1996-11-19
申请号：US766647
申请日：1991-09-26
申请人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
发明人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
CPC分类号： H04J3/0688 , G06F1/04 , G06F1/08 , H04J3/0691 , H04L7/0337
摘要： A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.
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