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1.发明授权公开(公告)号：US07830392B1
公开(公告)日：2010-11-09
申请号：US11612415
申请日：2006-12-18
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： The number of crossbars in a graphics processing unit is reduced by assigning each of a plurality of pixels to one of a plurality of pixel shaders based at least in part on a location of each of the plurality of pixels within an image area, generating an attribute value for each of the plurality of pixels using the plurality of pixel shaders, mapping the attribute value of each of the plurality of pixels to one of a plurality of memory partitions, and storing the attribute values in the memory partitions according to the mapping. The attribute value generated by a particular one of the pixel shaders is mapped to the same one of the plurality of memory partitions.
摘要翻译： 至少部分地基于图像区域内的多个像素中的每一个的位置，将多个像素中的每一个分配给多个像素着色器中的每一个来减少图形处理单元中的交叉条的数量，生成属性 使用所述多个像素着色器对所述多个像素中的每一个使用所述多个像素的值，将所述多个像素中的每一个的属性值映射到多个存储器分区中的一个，并且根据所述映射将所述属性值存储在所述存储器分区中。 由特定的像素着色器生成的属性值被映射到多个存储器分区中的相同的一个。
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公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译： 用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。 耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。
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公开(公告)号：US08730249B2
公开(公告)日：2014-05-20
申请号：US13269462
申请日：2011-10-07
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译： 用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。 耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。
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4.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。
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5.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。
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公开(公告)号：US06992669B2
公开(公告)日：2006-01-31
申请号：US10198707
申请日：2002-07-17
IPC分类号： G06T17/00
CPC分类号： G06T11/40 , G06T15/005 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the graphics data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data received from the lighting module. During use, an antialiasing feature is implemented on the single semiconductor platform to improve a quality of the graphics rendering.
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7.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记 基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性 公共输入流。 每个片段流被独立地处理并对应于其中一个ROP请求流。
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公开(公告)号：US08493395B2
公开(公告)日：2013-07-23
申请号：US13550468
申请日：2012-07-16
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。
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9.发明授权Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation 有权用于在图形系统中使用页表条目以提供用于地址转换的存储格式信息的装置，系统和方法公开(公告)号：US07859541B2
公开(公告)日：2010-12-28
申请号：US12479571
申请日：2009-06-05
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
摘要翻译： 图形系统利用页表条目来提供用于存储图形数据的存储格式的信息。 页表条目又可用于地址转换。 存储格式信息的示例性种类包括压缩模式，用于存储瓦片中的Z数据的打包模式或瓦片中的颜色数据，以及用于在分区存储器中的分区之间分配瓦片数据的模式。
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10.发明授权公开(公告)号：US08228338B1
公开(公告)日：2012-07-24
申请号：US11625136
申请日：2007-01-19
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。
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