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1.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记 基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性 公共输入流。 每个片段流被独立地处理并对应于其中一个ROP请求流。
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2.发明授权公开(公告)号：US07999820B1
公开(公告)日：2011-08-16
申请号：US11953812
申请日：2007-12-10
CPC分类号： G06F12/0223 , G06F12/10 , G09G5/39 , G09G2360/122
摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
摘要翻译： 公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。 本发明的一个实施例提出了一种方法，其包括将显示屏幕上的占位面积映射到存储器系统中的一组连续物理存储器位置，从与所述覆盖区相关联的第一事务确定锚物理存储器地址，其中， 锚物理存储器地址对应于连续物理存储器位置组中的锚点，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位（LSB），以及组合锚物理 存储器地址与与第二事务相关联的一组LSB产生用于第二事务的第二物理存储器地址，从而避免第二次完全地址转换。
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公开(公告)号：US08232991B1
公开(公告)日：2012-07-31
申请号：US11934042
申请日：2007-11-01
CPC分类号： G06T15/40
摘要： The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
摘要翻译： 当本发明涉及当将存储器组织在可能不匹配着色器数量的多个分区中时，用于计算每个样本后z测试覆盖的新系统和方法。 着色器输出的阴影像素可以由几个z光栅操作单元之一处理。 可以独立于存储器分区的数量和z光栅操作单元的数量来配置着色处理能力。 本发明还涉及使用具有单个或多个存储器分区的具有多个渲染目标的不同z测试模式的新系统和方法。 渲染性能可以通过使用早期z测试模式来改善，用于在阴影之前消除不可见样本。
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公开(公告)号：US08228328B1
公开(公告)日：2012-07-24
申请号：US11934046
申请日：2007-11-01
CPC分类号： G06T15/40
摘要： The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
摘要翻译： 当本发明涉及当将存储器组织在可能不匹配着色器数量的多个分区中时，用于计算每个样本后z测试覆盖的新系统和方法。 着色器输出的阴影像素可以由几个z光栅操作单元之一处理。 可以独立于存储器分区的数量和z光栅操作单元的数量来配置着色处理能力。 本发明还涉及使用具有单个或多个存储器分区的具有多个渲染目标的不同z测试模式的新系统和方法。 渲染性能可以通过使用早期z测试模式来改善，用于在阴影之前消除不可见样本。
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公开(公告)号：US08933933B2
公开(公告)日：2015-01-13
申请号：US11430635
申请日：2006-05-08
申请人： Mark J. French , Emmett M. Kilgariff , Steven E. Molnar , Walter R. Steiner , Douglas A. Voorhies , Adam Clark Weitkemper
发明人： Mark J. French , Emmett M. Kilgariff , Steven E. Molnar , Walter R. Steiner , Douglas A. Voorhies , Adam Clark Weitkemper
CPC分类号： G06T15/405 , G06T15/005
摘要： One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.
摘要翻译： 本发明的一个实施例阐述了在可能的情况下在像素着色之前推进Z检验操作的架构。 由设置引擎维护的当前呈现状态确定是否可以在着色引擎之上前进Z检验功能以进行“早期”Z检验，或者Z检验功能是否应该延迟到“晚期”的阴影操作之后 “Z测试。 数据在流水线中动态地路由到每个处理引擎，以便由当前呈现状态确定的早期Z或后期Z的适当数据流是动态构造的。 早期Z和晚期Z配置都使用相同的功能单元。
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公开(公告)号：US08243069B1
公开(公告)日：2012-08-14
申请号：US11934051
申请日：2007-11-01
CPC分类号： G06T15/40
摘要： The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
摘要翻译： 当本发明涉及当将存储器组织在可能不匹配着色器数量的多个分区中时，用于计算每个样本后z测试覆盖的新系统和方法。 着色器输出的阴影像素可以由几个z光栅操作单元之一处理。 可以独立于存储器分区的数量和z个光栅操作单元的数量来配置着色处理能力。 本发明还涉及使用具有单个或多个存储器分区的具有多个渲染目标的不同z测试模式的新系统和方法。 渲染性能可以通过使用早期z测试模式来改善，用于在阴影之前消除不可见样本。
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公开(公告)号：US07626588B1
公开(公告)日：2009-12-01
申请号：US11454225
申请日：2006-06-16
申请人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
发明人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
CPC分类号： G06F12/0802 , G06T1/60 , G06T11/40 , G09G2360/121
摘要： Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached tiles. Each of these cached tiles has a certain priority to remain in the local cache, with the priority corresponding to a conflict type received from a buffer operating within a pre-raster engine operations stage of the graphics rendering pipeline.
摘要翻译： 公开了高级缓存管理方法和系统。 在一个实施例中，在图形渲染流水线的光栅引擎操作阶段内操作的本地高速缓存通过跟随与多个缓存的瓦片相关的多个缓存判定来管理。 这些缓存的瓦片中的每一个具有保留在本地高速缓存中的一定优先级，其优先级对应于从在图形呈现流水线的前光栅引擎操作阶段内操作的缓冲器接收到的冲突类型。
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公开(公告)号：US07616209B1
公开(公告)日：2009-11-10
申请号：US11454230
申请日：2006-06-16
申请人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
发明人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
CPC分类号： G09G5/363 , G06T1/60 , G06T11/40 , G09G5/39 , G09G2360/121 , G09G2360/122
摘要： Prescient cache management methods and systems are disclosed. In one embodiment, within a pre-raster engine operations stage in a graphics rendering pipeline, tile entries are stored in a buffer. Each of these tile entries is related a transaction request that enters the pre-raster engine operations stage and has a screen coordinates field and a conflict field. If this buffer includes a first tile entry, which is related to a first transaction request associated with a first tile, and a second tile entry, which is related to a second transaction request that enters the pre-raster engine operations stage after the first transaction request and is also associated with the first tile, the conflict field of the first tile entry is updated with a conflict type that reflects a number of tile entries between the first tile entry and the second tile entry.
摘要翻译： 公开了高级缓存管理方法和系统。 在一个实施例中，在图形渲染流水线的光栅前引擎操作阶段内，瓦片条目被存储在缓冲器中。 这些瓦片条目中的每一个都与进入光栅前引擎操作阶段并具有屏幕坐标字段和冲突字段的事务请求相关联。 如果该缓冲器包括第一瓦片条目，其与与第一瓦片相关联的第一事务请求和第二瓦片条目相关，第二瓦片条目与在第一交易之后进入前光栅引擎操作阶段的第二事务请求相关 请求并且还与第一瓦片相关联，用反映第一瓦片条目和第二瓦片条目之间的多个瓦片条目的冲突类型来更新第一瓦片条目的冲突字段。
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