公开(公告)号：US6105051A

公开(公告)日：2000-08-15

申请号：US956875

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06567839B1

公开(公告)日：2003-05-20

申请号：US08957002

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储可以发生线程切换的条件。 在发生线程切换事件时，动态询问所有线程的状态和优先级，以确定哪个线程应该是执行处理器的主动线程。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程开关逻辑还响应于能够改变不同线程的优先级并因此取代线程切换事件的线程切换管理器。

公开(公告)号：US6076157A

公开(公告)日：2000-06-13

申请号：US956577

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/44 ,  G06F9/24

CPC分类号： G06F9/4825 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06697935B1

公开(公告)日：2004-02-24

申请号：US08958716

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F1500

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US07877580B2

公开(公告)日：2011-01-25

申请号：US11953799

申请日：2007-12-10

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/00

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages.

摘要翻译： 一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令 条件，并确定投机执行使用的数据的有效性。 调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。 指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性 流水线阶段

公开(公告)号：US20080250226A1

公开(公告)日：2008-10-09

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US06694425B1

公开(公告)日：2004-02-17

申请号：US09564930

申请日：2000-05-04

申请人： Richard James Eickemeyer

发明人： Richard James Eickemeyer

IPC分类号： G06F940

CPC分类号： G06F9/3851 ,  G06F9/3867

摘要： In a simultaneous multithread processor, a flush mechanism of a shared pipeline stage is disclosed. In the preferred embodiment, the shared pipeline stage happens to be one or all of the fetch stage, the decode stage, and/or the dispatch stage and the flush mechanism flushes instructions at the dispatch stage and earlier stages. The dispatch flush mechanism detects when an instruction of a particular thread is stalled at the dispatch stage of the pipelined processor. Subsequent instructions of that thread are flushed from all pipeline stages of the processor up to and including the dispatch stage. The dispatch stage is distinguished as being the stage in which all resources necessary for the successful dispatch of the instruction to the issue queues are checked. If a resource required only by that instruction is unavailable, then a dispatch flush is performed. Flush prioritization logic is available to determine if other flush conditions, including a previous dispatch flush, exist for that particular thread. If so, the flush prioritization logic will determine which flush, if any, should proceed. Those resources necessary for the successful dispatch and issuance of the instruction to the execution units but which are unavailable may be private or separate registers for each thread, may be special purpose or other non-renamed registers, or may be instructions for synchronized access to memory. This dispatch flush mechanism is more efficient than existing flush mechanisms which must flush throughout the processor pipelines up to and including the issue queues and execution units and result registers.

摘要翻译： 在同时多线程处理器中，公开了共享流水线级的冲洗机构。 在优选实施例中，共享流水线阶段恰好是提取阶段，解码阶段和/或调度阶段中的一个或全部，并且刷新机制在调度阶段和早期阶段刷新指令。 调度刷新机制检测在流水线处理器的调度阶段什么时候特定线程的指令停止。 该线程的后续指令从处理器的所有流水线阶段冲洗到并包括调度阶段。 调度阶段被区分为检查成功发送指令到发布队列所需的所有资源的阶段。 如果该指令所需的资源不可用，则执行调度刷新。 刷新优先级逻辑可用于确定是否存在针对该特定线程的其他刷新条件（包括先前的调度刷新）。 如果是这样，刷新优先级逻辑将确定哪个刷新（如果有的话）应该进行。 成功发送执行单元但不可用的指令所需的资源可以是每个线程的专用或单独的寄存器，可以是特殊目的或其他未重命名的寄存器，或者可以是同步访问存储器的指令 。 这种调度刷新机制比现有的刷新机制更有效，这些机制必须遍及整个处理器管道，直到并包括问题队列和执行单元和结果寄存器。

公开(公告)号：US06393552B1

公开(公告)日：2002-05-21

申请号：US09100718

申请日：1998-06-19

申请人： Richard James Eickemeyer ,  Nadeem Malik ,  Alan Vicha Pita ,  Avijit Saha

发明人： Richard James Eickemeyer ,  Nadeem Malik ,  Alan Vicha Pita ,  Avijit Saha

IPC分类号： G06F934

CPC分类号： G06F9/30109 ,  G06F9/384

摘要： A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

摘要翻译： 提供了一种方法和实现系统，其中处理器寄存器被划分为扇区，并且这些扇区被单独重命名。 在一个实施例中，寄存器文件被划分为扇区，使得每个寄存器中用于指令集的最小可访问单元可被唯一地寻址并重新命名，从而提供用于重命名的附加有效寄存器。

公开(公告)号：US5802564A

公开(公告)日：1998-09-01

申请号：US676785

申请日：1996-07-08

申请人： Richard James Eickemeyer ,  Nadeem Malik ,  Avijit Saha ,  Charles Gorham Ward

发明人： Richard James Eickemeyer ,  Nadeem Malik ,  Avijit Saha ,  Charles Gorham Ward

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/02 ,  G06F13/38

CPC分类号： G06F9/30134 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/383

摘要： A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

摘要翻译： 一种用于减少在具有中央处理单元（CPU）的数据处理系统中实现加载指令所需的周期数的方法和装置。 CPU包括通过加载指令的偏移字段索引的高速缓存寄存器文件，用于从先前执行的加载指令保留高速缓存行。 然后，缓存寄存器文件被要求其中预先加载的数据的后续指令（例如加载指令）使用。 因此，减少通常与随后的指令从高速缓存检索数据相关联的周期。

公开(公告)号：US07620799B2

公开(公告)日：2009-11-17

申请号：US12061290

申请日：2008-04-02

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838

摘要： Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons. Dependency and dirty bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers is used.

摘要翻译： 提供了在失速状态下识别和推测执行未来指令的机制。 在推测模式下，指令操作数可能因无数原因而无效。 跟踪依赖关系和脏位，并用于确定哪些推测指令对执行有效。 改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。 修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。 当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令中绕过的较小的推测指令使用该修改的数据。 否则，将使用来自架构寄存器的数据。