公开(公告)号：US6105051A

公开(公告)日：2000-08-15

申请号：US956875

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06567839B1

公开(公告)日：2003-05-20

申请号：US08957002

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储可以发生线程切换的条件。 在发生线程切换事件时，动态询问所有线程的状态和优先级，以确定哪个线程应该是执行处理器的主动线程。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程开关逻辑还响应于能够改变不同线程的优先级并因此取代线程切换事件的线程切换管理器。

公开(公告)号：US6076157A

公开(公告)日：2000-06-13

申请号：US956577

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/44 ,  G06F9/24

CPC分类号： G06F9/4825 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06697935B1

公开(公告)日：2004-02-24

申请号：US08958716

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F1500

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06212544B1

公开(公告)日：2001-04-03

申请号：US08958718

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F946

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US5790843A

公开(公告)日：1998-08-04

申请号：US718180

申请日：1996-09-19

申请人： John Michael Borkenhagen ,  William Thomas Flynn ,  Philip Rodgers Hillier, III ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  William Thomas Flynn ,  Philip Rodgers Hillier, III ,  Andrew Henry Wottreng

IPC分类号： G06F9/318 ,  G06F9/445 ,  G06F9/00

CPC分类号： G06F9/3017 ,  G06F8/66 ,  G06F9/328

摘要： Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize instruction match register/execution control register (IMR/ECR) pairs to first identify known problematic instructions and to then alter control of the microprocessor in a preselected manner when processing each problematic instruction. The invention contemplates the use of numerous control options for altering control of the microprocessor.

摘要翻译： 这里描述了一种用于在微处理器设备上提供依赖于指令的执行控制的系统和方法。 系统和方法利用指令匹配寄存器/执行控制寄存器（IMR / ECR）对来首先识别已知的有问题的指令，然后在处理每个有问题的指令时以预先选择的方式改变微处理器的控制。 本发明考虑使用许多控制选项来改变微处理器的控制。

公开(公告)号：US07865757B2

公开(公告)日：2011-01-04

申请号：US12018359

申请日：2008-01-23

申请人： John Michael Borkenhagen ,  Benjamin F. Carter, III ,  Stephen Roland Levesque

发明人： John Michael Borkenhagen ,  Benjamin F. Carter, III ,  Stephen Roland Levesque

IPC分类号： G06F1/00 ,  G06F1/04

CPC分类号： G06F9/5061

摘要： An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

摘要翻译： 公开了一种用于通过使用控制改变计算机系统中的信令总线上的延迟和/或带宽来提供按需容量的装置和方法。 如果需要额外的容量，则需要授权额外的容量。 如果被授权，增加信令总线的带宽以在计算系统中提供额外的容量。 或者，经授权，减少了通过信令总线的数据传输的延迟。 在另一个替代方案中，经过授权，调整存储器定时以加速存储器获取和存储。

公开(公告)号：US07707463B2

公开(公告)日：2010-04-27

申请号：US11290894

申请日：2005-11-30

申请人： Gerald Keith Bartley ,  John Michael Borkenhagen ,  William Paul Hovis ,  Daniel Paul Kolz

发明人： Gerald Keith Bartley ,  John Michael Borkenhagen ,  William Paul Hovis ,  Daniel Paul Kolz

IPC分类号： G06F11/00

CPC分类号： G06F11/1064 ,  G06F12/082

摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.

摘要翻译： 提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。 目录包括用户选择的操作模式，包括演奏模式和可靠性模式。 在可靠性模式下，更多的目录位用于纠错和检测。 在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

公开(公告)号：US20090164990A1

公开(公告)日：2009-06-25

申请号：US11959473

申请日：2007-12-19

申请人： Shmuel Ben-Yehuda ,  John Michael Borkenhagen

发明人： Shmuel Ben-Yehuda ,  John Michael Borkenhagen

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/545 ,  G06F9/45558 ,  G06F2009/45579

摘要： The present invention implements a mechanism to decide when it is beneficial to switch from the current virtual input/output mechanism to a different one. The present invention determines which input/output mechanism each virtual machine should use based on the available input/output resources of the virtual machines (with their respective available input/output adapters), the number of virtual machines running and their input/output needs, and the input/output needs of the virtual machine being considered. The present invention also provides a mechanism for virtual machine to seamlessly switch input/output mechanisms. When beneficial, the standard hot-plug mechanism of the virtual machine and the hypervisor is used to first remove the existing input/output mechanism and then add the new input/output mechanism.

摘要翻译： 本发明实现了一种机制，用于决定什么时候从当前的虚拟输入/输出机制切换到不同的虚拟输入/输出机制是有益的。 本发明基于虚拟机（其各自的可用输入/输出适配器）的可用输入/输出资源，运行的虚拟机的数量及其输入/输出需求来确定每个虚拟机应该使用哪个输入/输出机制， 并考虑虚拟机的输入/输出需求。 本发明还提供了一种用于虚拟机无缝切换输入/输出机制的机制。 有利的是，使用虚拟机和管理程序的标准热插拔机制来首先删除现有的输入/输出机制，然后添加新的输入/输出机制。

公开(公告)号：US07526692B2

公开(公告)日：2009-04-28

申请号：US10955735

申请日：2004-09-30

申请人： John Michael Borkenhagen ,  William Paul Hovis ,  James Anthony Marcella ,  Paul Rudrud

发明人： John Michael Borkenhagen ,  William Paul Hovis ,  James Anthony Marcella ,  Paul Rudrud

IPC分类号： G01R31/28

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/5602

摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

摘要翻译： 用于存储器设备的诊断接口架构在一个方面支持通常与从存储器件读取数据和/或将数据写入存储器件一起使用的一个或多个动态可重新配置的功能互连。 动态可重构功能互连能够被配置为以功能或诊断模式操作，由此在诊断模式中，这种互连可以用于传送诊断信息以支持一个或多个诊断操作。 诊断接口架构还可以支持给定存储器设备中的多个诊断接口，其中至少一个这样的诊断接口能够响应于另一诊断接口中的故障被选择性地启用。