公开(公告)号：US6105051A

公开(公告)日：2000-08-15

申请号：US956875

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06567839B1

公开(公告)日：2003-05-20

申请号：US08957002

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储可以发生线程切换的条件。 在发生线程切换事件时，动态询问所有线程的状态和优先级，以确定哪个线程应该是执行处理器的主动线程。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程开关逻辑还响应于能够改变不同线程的优先级并因此取代线程切换事件的线程切换管理器。

公开(公告)号：US6076157A

公开(公告)日：2000-06-13

申请号：US956577

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/44 ,  G06F9/24

CPC分类号： G06F9/4825 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06697935B1

公开(公告)日：2004-02-24

申请号：US08958716

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F1500

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06212544B1

公开(公告)日：2001-04-03

申请号：US08958718

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F946

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US5790843A

公开(公告)日：1998-08-04

申请号：US718180

申请日：1996-09-19

申请人： John Michael Borkenhagen ,  William Thomas Flynn ,  Philip Rodgers Hillier, III ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  William Thomas Flynn ,  Philip Rodgers Hillier, III ,  Andrew Henry Wottreng

IPC分类号： G06F9/318 ,  G06F9/445 ,  G06F9/00

CPC分类号： G06F9/3017 ,  G06F8/66 ,  G06F9/328

摘要： Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize instruction match register/execution control register (IMR/ECR) pairs to first identify known problematic instructions and to then alter control of the microprocessor in a preselected manner when processing each problematic instruction. The invention contemplates the use of numerous control options for altering control of the microprocessor.

摘要翻译： 这里描述了一种用于在微处理器设备上提供依赖于指令的执行控制的系统和方法。 系统和方法利用指令匹配寄存器/执行控制寄存器（IMR / ECR）对来首先识别已知的有问题的指令，然后在处理每个有问题的指令时以预先选择的方式改变微处理器的控制。 本发明考虑使用许多控制选项来改变微处理器的控制。

公开(公告)号：US06256775B1

公开(公告)日：2001-07-03

申请号：US08989220

申请日：1997-12-11

申请人： William Thomas Flynn

发明人： William Thomas Flynn

IPC分类号： G06F9445

CPC分类号： G06F11/3466 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/542 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： A method, apparatus, and article of manufacture for monitoring performance of an application or a system program executed by a multithreaded processor arranged and configured to process a plurality of threads and facilitate thread switch. The low-level invisible events, such as cache misses, or other events of interest of an application or a system program, are detected and recorded by using a software monitor program running on a thread of the multithreaded processor via thread switching techniques. The monitoring thread gains control once a selected event is detected while executing the application or system program, and it relinquishes the control after completing the recording of the selected event. The recorded information allows one to dynamically profile the application or the system program and to provide insight into the performance characteristics of the application or the system program.

摘要翻译： 一种用于监视被布置和配置为处理多个线程并促进线程切换的多线程处理器执行的应用或系统程序的性能的方法，装置和制品。 通过使用通过线程切换技术在多线程处理器的线程上运行的软件监视程序来检测和记录低级不可见事件，例如高速缓存未命中或应用程序或系统程序感兴趣的其他事件。 一旦在执行应用程序或系统程序时检测到所选事件，监控线程就会获得控制权，并且在完成所选事件的记录之后放弃控制。 所记录的信息可以使应用程序或系统程序动态配置，并提供洞察应用程序或系统程序的性能特征。

公开(公告)号：US08358658B2

公开(公告)日：2013-01-22

申请号：US12727545

申请日：2010-03-19

申请人： William Thomas Flynn ,  Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： William Thomas Flynn ,  Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/28

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

公开(公告)号：US08514885B2

公开(公告)日：2013-08-20

申请号：US12749812

申请日：2010-03-30

申请人： William Thomas Flynn ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： William Thomas Flynn ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04J3/16 ,  H04J3/22 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

CPC分类号： H04L1/0079 ,  H03M13/09 ,  H04L1/0072

摘要： A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.

摘要翻译： 一种用于实现可变长度分组以在互连系统中嵌入额外控制信息的方法和电路，以及提供了主题电路所在的设计结构。 分组被定义为在分组报头中的分组（Flit）计数字段内包括端到端（ETE）流单元。 分组报头还包括其自己的CRC字段。 当在来自传入链路的传入分组中接收到非零的ETE飞行计数字段时，从分组中删除指定数量的嵌入式ETE飞行，并且与控制信息到达自己的分组一样被使用。

公开(公告)号：US20110228783A1

公开(公告)日：2011-09-22

申请号：US12727545

申请日：2010-03-19

申请人： William Thomas Flynn ,  Philip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： William Thomas Flynn ,  Philip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/56

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。