公开(公告)号：US6163867A

公开(公告)日：2000-12-19

申请号：US141957

申请日：1998-08-28

申请人： John Miller ,  Richard Ortiz ,  Chenmin Zhang

发明人： John Miller ,  Richard Ortiz ,  Chenmin Zhang

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318525

摘要： A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.

摘要翻译： 用于测试集成器件（如印刷电路板上使用的芯片）的方法和系统。 该系统包括芯片上形成的耦合到双向输入/输出焊盘的测试逻辑。 该系统能够通过将来自一对焊盘的一个焊盘的输入测试信号耦合到该对焊盘的第二焊盘的输出来测试输入焊盘，输出焊盘和双向焊盘。 如果从第二衬垫读出的信号对应于期望值，则可以认为衬垫被正确连接。 芯片可以在芯片制造期间的任何阶段进行测试，包括在晶片上形成芯片之后，在晶片上切割晶片之后，以及在封装晶粒以产生芯片之后，以及将芯片附接到印刷电路板之后进行测试。 该系统和方法允许在制造过程中快速和容易地测试焊盘连接性，同时最小化芯片上的额外栅极和迹线的数量。

公开(公告)号：US20050097372A1

公开(公告)日：2005-05-05

申请号：US10698900

申请日：2003-10-31

申请人： Richard Ortiz ,  Roy Tsuchida ,  Walter Alexander ,  Jerry Huang

发明人： Richard Ortiz ,  Roy Tsuchida ,  Walter Alexander ,  Jerry Huang

IPC分类号： G06F1/30 ,  G06F1/18 ,  G06F1/26

CPC分类号： G06F1/26

摘要： Embodiments of the present invention include a method for providing protected swapping of a peripheral component in a computer system. The method comprises determining a position of a first mechanical retention latch wherein the first mechanical retention latch has an open position and a closed position and is configured to communicatively couple to a computer expansion card slot. Provided the first mechanical retention latch is in the open position, the method further includes filtering power management events and preventing the computer system from powering up. Provided the first mechanical retention latch is in the closed position, allowing the computer system to accept power management events.

摘要翻译： 本发明的实施例包括一种用于在计算机系统中提供周边组件的保护交换的方法。 该方法包括确定第一机械保持闩锁的位置，其中第一机械保持闩锁具有打开位置和关闭位置，并且被配置为可通信地耦合到计算机扩展卡槽。 如果第一机械保持闩锁处于打开位置，该方法还包括过滤电源管理事件并防止计算机系统上电。 如果第一个机械保持闩锁处于关闭位置，则允许计算机系统接受电源管理事件。

公开(公告)号：US07234013B2

公开(公告)日：2007-06-19

申请号：US10698900

申请日：2003-10-31

申请人： Richard Ortiz ,  Roy Tsuchida ,  Walter William Alexander, III ,  Jerry Huang

发明人： Richard Ortiz ,  Roy Tsuchida ,  Walter William Alexander, III ,  Jerry Huang

IPC分类号： G06F13/00

CPC分类号： G06F1/26

摘要： Embodiments of the present invention include a method for providing protected swapping of a peripheral component in a computer system. The method comprises determining a position of a first mechanical retention latch wherein the first mechanical retention latch has an open position and a closed position and is configured to communicatively couple to a computer expansion card slot. Provided the first mechanical retention latch is in the open position, the method further includes filtering power management events and preventing the computer system from powering up. Provided the first mechanical retention latch is in the closed position, allowing the computer system to accept power management events.

摘要翻译： 本发明的实施例包括一种用于在计算机系统中提供周边组件的保护交换的方法。 该方法包括确定第一机械保持闩锁的位置，其中第一机械保持闩锁具有打开位置和关闭位置，并且被配置为可通信地耦合到计算机扩展卡槽。 如果第一机械保持闩锁处于打开位置，该方法还包括过滤电源管理事件并防止计算机系统上电。 如果第一个机械保持闩锁处于关闭位置，则允许计算机系统接受电源管理事件。

公开(公告)号：US20050172176A1

公开(公告)日：2005-08-04

申请号：US10759362

申请日：2004-01-16

申请人： Richard Ortiz ,  Zane Westover ,  Roy Tsuchida ,  Dick Fong ,  Gregory Hargis

发明人： Richard Ortiz ,  Zane Westover ,  Roy Tsuchida ,  Dick Fong ,  Gregory Hargis

IPC分类号： G06F11/00 ,  G06F11/24

CPC分类号： G06F11/24

摘要： A method of verifying a monitoring and responsive infrastructure of a system is provided and described. The method includes setting a sensor to a simulation mode. Further, a test value is provided to simulate a real value outputted by the sensor. While in the simulation mode, the test value instead of the real value is sent to the monitoring and responsive infrastructure to invoke a response. Moreover, the response to the test value is verified. In an embodiment, the monitoring and responsive infrastructure is compliant with an Intelligent Platform Management Interface specification.

摘要翻译： 提供并描述了一种验证系统的监控和响应基础设施的方法。 该方法包括将传感器设置为模拟模式。 此外，提供测试值以模拟由传感器输出的实际值。 在模拟模式下，测试值而不是实际值被发送到监视和响应基础设施来调用响应。 此外，验证对测试值的响应。 在一个实施例中，监视和响应基础设施符合智能平台管理接口规范。