公开(公告)号：US20240221825A1

公开(公告)日：2024-07-04

申请号：US18396222

申请日：2023-12-26

申请人： John R. Riley ,  Anandraj Devarajan ,  Feroze Merchant ,  Amlan Ghosh

发明人： John R. Riley ,  Anandraj Devarajan ,  Feroze Merchant ,  Amlan Ghosh

IPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

摘要： Various embodiments provide apparatuses, systems, and methods for a register file array with a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL). A merge circuitry may include a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node. Read circuitry may be coupled to the LBL merge node to read data from a first memory cell via the selected LBL. In some embodiments, the LBL may be precharged to a supply voltage (e.g., Vcc) minus a threshold voltage, Vt, of the multiplexer transistor, as opposed to being precharged to Vcc as in prior techniques. Other embodiments may be described and claimed.

公开(公告)号：US20240005982A1

公开(公告)日：2024-01-04

申请号：US17852569

申请日：2022-06-29

申请人： Amlan Ghosh ,  John R. Riley ,  Feroze Merchant ,  Jaydeep Kulkarni

发明人： Amlan Ghosh ,  John R. Riley ,  Feroze Merchant ,  Jaydeep Kulkarni

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/11

CPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/1116 ,  H01L27/1104

摘要： A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.

公开(公告)号：US08526256B2

公开(公告)日：2013-09-03

申请号：US13234218

申请日：2011-09-16

申请人： Amlan Ghosh ,  Jente B. Kuang

发明人： Amlan Ghosh ,  Jente B. Kuang

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C7/067

摘要： A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.

摘要翻译： 提供了一种读出放大器，其包括响应于接收到设置信号以打开设备设备和预充电电压电平读取位线信号，保持器设备响应于从反相放大器接收低电平信号而接通，并且将上拉 电压在第一节点处，使得HIGH信号被输出到全局位线。 响应于接收所设置的信号以使所述设置装置和读取的位线信号通过读取堆叠路径放电到地并且响应于读取位线信号放电低于第一预先设计的电压电平，读取辅助装置在 读出放大器响应于从反相放大器接收到高电平信号并且降低第一节点处的电压而导通，使得LOW状态输出到全局位线。

公开(公告)号：US20130070549A1

公开(公告)日：2013-03-21

申请号：US13234218

申请日：2011-09-16

申请人： Amlan Ghosh ,  Jente B. Kuang

发明人： Amlan Ghosh ,  Jente B. Kuang

IPC分类号： G11C7/12

CPC分类号： G11C11/412 ,  G11C7/067

摘要： A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.

摘要翻译： 提供了一种读出放大器，其包括响应于接收到设置信号以打开设备设备和预充电电压电平读取位线信号，保持器设备响应于从反相放大器接收低电平信号而接通，并且将上拉 电压在第一节点处，使得HIGH信号被输出到全局位线。 响应于接收所设置的信号以使所述设置装置和读取的位线信号通过读取堆叠路径放电到地并且响应于读取位线信号放电低于第一预先设计的电压电平，读取辅助装置在 读出放大器响应于从反相放大器接收到高电平信号并且降低第一节点处的电压而导通，使得LOW状态输出到全局位线。

公开(公告)号：US07548822B2

公开(公告)日：2009-06-16

申请号：US11777329

申请日：2007-07-13

申请人： Ching-Te K. Chuang ,  Amlan Ghosh ,  Jae-Joon Kim ,  Rahul M. Rao

发明人： Ching-Te K. Chuang ,  Amlan Ghosh ,  Jae-Joon Kim ,  Rahul M. Rao

IPC分类号： G01R19/00

CPC分类号： G01R31/31932 ,  G01R31/3004 ,  G01R31/3016 ,  G01R31/31708 ,  G01R31/31937 ,  H03K3/356113 ,  H03K5/04

摘要： Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.

摘要翻译： 通过将信号与第一参考电压进行比较来确定来自被测集成电路的信号的转换速率，将信号与不同于第一参考电压的第二参考电压进行比较，产生具有指示转换的脉冲宽度的输出脉冲 信号的速率，并且随着时间积分输出脉冲以产生与脉冲宽度成比例的输出电压; 其中所述输出电压指示由所述集成电路产生的信号的转换速率。

公开(公告)号：US20090018787A1

公开(公告)日：2009-01-15

申请号：US11777329

申请日：2007-07-13

申请人： Ching-Te K. Chuang ,  Amlan Ghosh ,  Jae-Joon Kim ,  Rahul M. Rao

发明人： Ching-Te K. Chuang ,  Amlan Ghosh ,  Jae-Joon Kim ,  Rahul M. Rao

IPC分类号： G01R29/02 ,  H03K12/00 ,  H03K3/017

CPC分类号： G01R31/31932 ,  G01R31/3004 ,  G01R31/3016 ,  G01R31/31708 ,  G01R31/31937 ,  H03K3/356113 ,  H03K5/04

摘要： Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.

摘要翻译： 通过将信号与第一参考电压进行比较来确定来自被测集成电路的信号的转换速率，将信号与不同于第一参考电压的第二参考电压进行比较，产生具有指示转换的脉冲宽度的输出脉冲 信号的速率，并且随着时间积分输出脉冲以产生与脉冲宽度成比例的输出电压; 其中所述输出电压指示由所述集成电路产生的信号的转换速率。