公开(公告)号：US08086917B2

公开(公告)日：2011-12-27

申请号：US12542187

申请日：2009-08-17

Applicant: Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

Inventor： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

Abstract translation: 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US20090091346A1

公开(公告)日：2009-04-09

申请号：US11866502

申请日：2007-10-03

Applicant: Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

Inventor： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC: G01R31/26

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

Abstract translation: 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差 在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US07085798B2

公开(公告)日：2006-08-01

申请号：US10167276

申请日：2002-06-10

Applicant: Jae-Joon Kim ,  Ching-Te K. Chuang ,  Rajiv V. Joshi ,  Kaushik Roy

Inventor： Jae-Joon Kim ,  Ching-Te K. Chuang ,  Rajiv V. Joshi ,  Kaushik Roy

IPC: G06F7/50

CPC classification number: G06F7/508

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

公开(公告)号：US08217427B2

公开(公告)日：2012-07-10

申请号：US11865780

申请日：2007-10-02

Applicant: Ching-Te K. Chuang ,  Fadi H. Gebara ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung C. Ngo

Inventor： Ching-Te K. Chuang ,  Fadi H. Gebara ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung C. Ngo

IPC: H01L27/11

CPC classification number: H01L27/11 ,  H01L27/0207 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78648 ,  Y10S257/905

Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

Abstract translation: 存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。 每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件 晶体管和至少第一p型场效应晶体管。 所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有较薄的掩埋氧化物层。

公开(公告)号：US08139400B2

公开(公告)日：2012-03-20

申请号：US12017404

申请日：2008-01-22

Applicant: Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

Inventor： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC: G11C11/00 ,  H01L29/02

CPC classification number: G11C11/412

Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

Abstract translation: 存储器电路包括多个位线结构（每个都包括真和互补位线），与多个位线结构相交以形成多个单元位置的多个字线结构和位于该位线的多个单元 多个单元位置。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US20110173577A1

公开(公告)日：2011-07-14

申请号：US12024390

申请日：2008-02-01

Applicant: Ching-Te K. Chuang ,  Fook-Luen Heng ,  Rouwaida Kanj ,  Keunwoo Kim ,  Jin-Fuw Lee ,  Saibal Mukhopadhyay ,  Sani Richard Nassif ,  Rama Nand Singh

Inventor： Ching-Te K. Chuang ,  Fook-Luen Heng ,  Rouwaida Kanj ,  Keunwoo Kim ,  Jin-Fuw Lee ,  Saibal Mukhopadhyay ,  Sani Richard Nassif ,  Rama Nand Singh

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/10

Abstract: Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.

Abstract translation: 提供了改进电路设计和生产的技术。 一方面，提供了一种用于虚拟制造过程敏感电路的方法。 该方法包括以下步骤。 基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。 基于质量的度量用于为制造的电路的虚拟表示投影产量。 物理布局图和/或生产过程被修改。 重复获得，使用和修改步骤，直到达到期望的预计产量。

公开(公告)号：US20090185409A1

公开(公告)日：2009-07-23

申请号：US12017404

申请日：2008-01-22

Applicant: Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

Inventor： Aditya Bansal ,  Ching-Te K. Chuang ,  Jae-Joon Kim ,  Shih-Hsien Lo ,  Rahul M. Rao

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

Abstract translation: 存储器电路包括多个位线结构（每个都包括真和互补位线），与多个位线结构相交以形成多个单元位置的多个字线结构和位于该位线的多个单元 多个单元位置。 每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管 元件。 第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。 还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

公开(公告)号：US06952113B2

公开(公告)日：2005-10-04

申请号：US10644211

申请日：2003-08-20

Applicant: Richard B. Brown ,  Ching-Te K. Chuang ,  Peter W. Cook ,  Koushik K. Das ,  Rajiv V. Joshi

Inventor： Richard B. Brown ,  Ching-Te K. Chuang ,  Peter W. Cook ,  Koushik K. Das ,  Rajiv V. Joshi

IPC: H03K19/00 ,  A03K19/003

CPC classification number: H03K19/0016

Abstract: A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

Abstract translation: 具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。 电路逻辑电路和电源连接（V SUB）和GND之间的可选供电开关器件（NFET和/或PFET）的电路具有比正常电路器件更高的阈值。 当供电开关装置打开时，一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

公开(公告)号：US06816824B2

公开(公告)日：2004-11-09

申请号：US09294178

申请日：1999-04-19

Applicant: Ching-Te K. Chuang ,  Brian W. Curran ,  George E. Smith, III

Inventor： Ching-Te K. Chuang ,  Brian W. Curran ,  George E. Smith, III

IPC: G06F1750

CPC classification number: G06F17/5036

Abstract: Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

公开(公告)号：US06789099B2

公开(公告)日：2004-09-07

申请号：US10167170

申请日：2002-06-10

Applicant: Jae-Joon Kim ,  Ching-Te K. Chuang ,  Rajiv V. Joshi ,  Kaushik Roy

Inventor： Jae-Joon Kim ,  Ching-Te K. Chuang ,  Rajiv V. Joshi ,  Kaushik Roy

IPC: G06F750

CPC classification number: G06F7/508 ,  G06F7/503 ,  G06F7/507 ,  G06F2207/3872 ,  G06F2207/4814

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.