公开(公告)号：US07315301B1

公开(公告)日：2008-01-01

申请号：US11279981

申请日：2006-04-17

申请人： John V. Sell

发明人： John V. Sell

IPC分类号： G06T15/00

CPC分类号： G06T15/405

摘要： A computer graphics processing system includes a graphics processor and a computer memory responsive to the graphics processor. The computer memory includes an image depth buffer and a hierarchical image depth buffer. The hierarchical image depth buffer contains data items that identify a nearest depth value and a farthest depth value for a plurality of image depth buffer entries associated with a plurality of corresponding pixels.

摘要翻译： 计算机图形处理系统包括响应于图形处理器的图形处理器和计算机存储器。 计算机存储器包括图像深度缓冲器和分层图像深度缓冲器。 分层图像深度缓冲器包含标识与多个对应像素相关联的多个图像深度缓冲器条目的最近深度值和最远深度值的数据项。

公开(公告)号：US20120159090A1

公开(公告)日：2012-06-21

申请号：US12970361

申请日：2010-12-16

申请人： Jeffrey Andrews ,  John V. Sell ,  Susan Carrie ,  Mark S. Grossman ,  John Tardif ,  Nicholas R. Baker

发明人： Jeffrey Andrews ,  John V. Sell ,  Susan Carrie ,  Mark S. Grossman ,  John Tardif ,  Nicholas R. Baker

IPC分类号： G06F12/00

CPC分类号： G06F9/5061 ,  G06T1/20

摘要： Versions of a multimedia computer system architecture are described which satisfy quality of service (QoS) guarantees for multimedia applications such as game applications while allowing platform resources, hardware resources in particular, to scale up or down over time. Computing resources of the computer system are partitioned into a platform partition and an application partition, each including its own central processing unit (CPU) and, optionally, graphics processing unit (GPU). To enhance scalability of resources up or down, the platform partition includes one or more hardware resources which are only accessible by the multimedia application via a software interface. Additionally, outside the partitions may be other resources shared by the partitions or which provide general purpose computing resources.

摘要翻译： 描述了多媒体计算机系统架构的版本，其满足诸如游戏应用的多媒体应用的服务质量（QoS）保证，同时允许平台资源，特别是硬件资源随着时间的推移或缩小。 计算机系统的计算资源被划分为平台分区和应用分区，每个分区包括其自己的中央处理单元（CPU）和可选的图形处理单元（GPU）。 为了提高或降低资源的可扩展性，平台分区包括只能通过软件界面由多媒体应用程序访问的一个或多个硬件资源。 另外，在分区之外可以是由分区共享的或提供通用计算资源的其他资源。

公开(公告)号：US07030877B1

公开(公告)日：2006-04-18

申请号：US10090507

申请日：2002-03-04

申请人： John V. Sell

发明人： John V. Sell

IPC分类号： G06T15/40

CPC分类号： G06T15/405

摘要： The present invention relates to a computer graphics processing system, a memory and a method for use in connection with the computer graphics processing system. In one embodiment, the computer graphics processing system includes a graphics processor and a computer memory responsive to the graphics processor. The computer memory includes an image depth buffer and a hierarchical image depth buffer. The hierarchical image depth buffer contains data items that identify a nearest depth value and a farthest depth value for a plurality of image depth buffer entries associated with a plurality of corresponding pixels. In one embodiment, the method is for use in rendering a portion of an object onto a two-dimensional image plane. A disclosed method includes the steps of identifying a selected pixel corresponding to the portion of the object to be rendered, reading data items from a hierarchical image depth buffer, and performing a comparison between the selected pixel and the data items to make a pixel visibility determination. The data items include a near depth value and a far depth value. The hierarchical image depth buffer is associated with a plurality of depth values for a set of pixels where the set of pixels includes the selected pixel.

摘要翻译： 本发明涉及计算机图形处理系统，存储器和与计算机图形处理系统结合使用的方法。 在一个实施例中，计算机图形处理系统包括响应于图形处理器的图形处理器和计算机存储器。 计算机存储器包括图像深度缓冲器和分层图像深度缓冲器。 分层图像深度缓冲器包含标识与多个对应像素相关联的多个图像深度缓冲器条目的最近深度值和最远深度值的数据项。 在一个实施例中，该方法用于将对象的一部分呈现到二维图像平面上。 所公开的方法包括以下步骤：识别与要渲染的对象的部分相对应的所选像素，从分层图像深度缓冲器读取数据项，以及执行所选择的像素与数据项之间的比较，以进行像素可视性确定 。 数据项包括近深度值和远深度值。 分层图像深度缓冲器与一组像素相关联的多个深度值，其中像素集合包括所选择的像素。

公开(公告)号：US07023445B1

公开(公告)日：2006-04-04

申请号：US10822506

申请日：2004-04-12

申请人： John V. Sell

发明人： John V. Sell

IPC分类号： G09G5/36

CPC分类号： G09G5/363 ,  G06F3/14 ,  G09G2360/121 ,  G09G2360/125

摘要： A method and mechanism for managing graphics data. A graphics unit is coupled to share a cache and a memory with a processor. The graphics unit is configured to partition rendered images into a plurality of subset areas. During the rendering of an image, data corresponding to subset areas of an image which require a relatively high number of accesses is deemed cacheable for a subsequent rendering. During a subsequent image rendering, if the graphics unit is required to evict data from a local buffer, the evicted data is only stored in the shared cache if a prior rendering indicated that the corresponding data is cacheable.

摘要翻译： 一种用于管理图形数据的方法和机制。 图形单元被耦合以与处理器共享高速缓存和存储器。 图形单元被配置为将呈现的图像分割成多个子集区域。 在渲染图像期间，对应于需要相对较高数量访问的图像的子集区域的数据被认为可缓存以用于随后的渲染。 在随后的图像渲染期间，如果图形单元被要求从本地缓冲器驱逐数据，则如果先前的渲染指示相应的数据是可高速缓存的，则被驱逐的数据仅被存储在共享高速缓存中。

公开(公告)号：US5860114A

公开(公告)日：1999-01-12

申请号：US942255

申请日：1997-10-01

申请人： John V. Sell

发明人： John V. Sell

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A plurality of "snoop advisory" bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective "snoop advisory page" of the memory address space. Three parallel processes take place with respect to these bits. First, in response to each read access by the processor structure, if the read access is of a predetermined type (such as a cache line fill operation with intent to modify), snoop management circuitry writes a "snoop yes" value into the snoop advisory cell corresponding to the snoop advisory page which includes the address of the processor's access. Second, in response to each access by another device which shares the address space with the processor structure, a snoop request is issued to the processor structure, but only if the snoop advisory cell corresponding to the snoop advisory page which includes the address of the device's access, contains the "snoop yes" value. Otherwise, the device is allowed to perform its access directly to the memory structure without issuing a snoop request. Third, on a recurrent basis, the processor internal cache is synchronized with the memory structure and the system writes a "snoop no" value into each of the snoop advisory bits to clear them. Synchronization can involve performing a write-back on each cache line which is in a modified state, and/or invalidating each line in the cache.

摘要翻译： 多个“窥探顾问”位由处理器结构外部的窥探管理电路维护。 每个窥探顾问位对应于存储器地址空间的相应“窥探顾问页”。 相对于这些位发生三个并行处理。 首先，响应于处理器结构的每次读取访问，如果读取访问是预定类型（例如意图修改的高速缓存线填充操作），则窥探管理电路将“窥探是”值写入窥探咨询 对应于包含处理器访问地址的窥探顾问页面的单元。 第二，响应于与处理器结构共享地址空间的另一设备的每个访问，向处理器结构发出窥探请求，但是只有当窥探顾问页面对应的窥探顾问单元包括设备的地址 访问，包含“snoop yes”值。 否则，允许该设备直接执行其对存储器结构的访问，而不发出窥探请求。 第三，在经常性的基础上，处理器内部缓存与存储器结构同步，并且系统向每个窥探顾问位写入“snoop no”值以清除它们。 同步可以涉及在处于修改状态的每个高速缓存线上执行回写，和/或使高速缓存中的每一行无效。