公开(公告)号：US20120159090A1

公开(公告)日：2012-06-21

申请号：US12970361

申请日：2010-12-16

申请人： Jeffrey Andrews ,  John V. Sell ,  Susan Carrie ,  Mark S. Grossman ,  John Tardif ,  Nicholas R. Baker

发明人： Jeffrey Andrews ,  John V. Sell ,  Susan Carrie ,  Mark S. Grossman ,  John Tardif ,  Nicholas R. Baker

IPC分类号： G06F12/00

CPC分类号： G06F9/5061 ,  G06T1/20

摘要： Versions of a multimedia computer system architecture are described which satisfy quality of service (QoS) guarantees for multimedia applications such as game applications while allowing platform resources, hardware resources in particular, to scale up or down over time. Computing resources of the computer system are partitioned into a platform partition and an application partition, each including its own central processing unit (CPU) and, optionally, graphics processing unit (GPU). To enhance scalability of resources up or down, the platform partition includes one or more hardware resources which are only accessible by the multimedia application via a software interface. Additionally, outside the partitions may be other resources shared by the partitions or which provide general purpose computing resources.

摘要翻译： 描述了多媒体计算机系统架构的版本，其满足诸如游戏应用的多媒体应用的服务质量（QoS）保证，同时允许平台资源，特别是硬件资源随着时间的推移或缩小。 计算机系统的计算资源被划分为平台分区和应用分区，每个分区包括其自己的中央处理单元（CPU）和可选的图形处理单元（GPU）。 为了提高或降低资源的可扩展性，平台分区包括只能通过软件界面由多媒体应用程序访问的一个或多个硬件资源。 另外，在分区之外可以是由分区共享的或提供通用计算资源的其他资源。

公开(公告)号：US20100275208A1

公开(公告)日：2010-10-28

申请号：US12429965

申请日：2009-04-24

申请人： Susan Carrie

发明人： Susan Carrie

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F15/00 ,  G06F12/00

CPC分类号： G06F8/451 ,  G06F9/5027

摘要： Software rendering and fine grained parallelism are utilized to reduce/ovoid memory latency in a multi-processor (MP) system. According to one embodiment, the management of the transfer of data from one processor to another in the MP environment is moved into a low overhead hardware system. The low overhead hardware system may be a FIFO (“First In First Out”) hardware control. Each FIFO may be real or virtual.

摘要翻译： 在多处理器（MP）系统中，利用软件渲染和细粒度并行来减少/卵形存储器延迟。 根据一个实施例，在MP环境中将数据从一个处理器传输到另一个处理器的管理被移动到低开销硬件系统中。 低开销硬件系统可以是FIFO（“先进先出”）硬件控制。 每个FIFO可以是真实的或虚拟的。

公开(公告)号：US20070006040A1

公开(公告)日：2007-01-04

申请号：US11170818

申请日：2005-06-30

申请人： Susan Carrie ,  Jeffrey Andrews

发明人： Susan Carrie ,  Jeffrey Andrews

IPC分类号： G06F11/00

CPC分类号： G06F11/3648

摘要： A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e.g., a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.

摘要翻译： 调试架构包括一组调试计数器，用于根据来自被监视设备的一组信号对一个或多个事件进行计数。 该架构提供了在设备运行期间观察调试计数器的输出。 在被监视的设备的操作期间，计数器的输出经由输出总线接口被提供给输出总线（例如，调试总线）。 数据采集​​系统可以访问输出总线，以便从计数器收集数据进行分析。

公开(公告)号：US20120272011A1

公开(公告)日：2012-10-25

申请号：US13090132

申请日：2011-04-19

申请人： Susan Carrie ,  Vijay Balakrishnan

发明人： Susan Carrie ,  Vijay Balakrishnan

IPC分类号： G06F12/08

CPC分类号： G06F11/3466 ,  G06F12/0802 ,  G06F2201/885

摘要： A method for refining multithread software executed on a processor chip of a computer system. The envisaged processor chip has at least one processor core and a memory cache coupled to the processor core and configured to cache at least some data read from memory. The method includes, in logic distinct from the processor core and coupled to the memory cache, observing a sequence of operations of the memory cache and encoding a sequenced data stream that traces the sequence of operations observed.

摘要翻译： 一种用于精炼在计算机系统的处理器芯片上执行的多线程软件的方法。 所设想的处理器芯片具有至少一个处理器核心和耦合到处理器核心的存储器高速缓存，并被配置为缓存从存储器读取的至少一些数据。 该方法在与处理器核心不同且耦合到存储器高速缓存的逻辑中包括：观察存储器高速缓存的操作序列并编码跟踪所观察操作序列的排序数据流。

公开(公告)号：US08239866B2

公开(公告)日：2012-08-07

申请号：US12429965

申请日：2009-04-24

申请人： Susan Carrie

发明人： Susan Carrie

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/54 ,  G06F7/00 ,  G06F9/00 ,  G06F9/44 ,  G06F13/00

CPC分类号： G06F8/451 ,  G06F9/5027

摘要： Software rendering and fine grained parallelism are utilized to reduce/avoid memory latency in a multi-processor (MP) system. According to one embodiment, the management of the transfer of data from one processor to another in the MP environment is moved into a low overhead hardware system. The low overhead hardware system may be a FIFO (“First In First Out”) hardware control. Each FIFO may be real or virtual.

摘要翻译： 利用软件渲染和细粒度并行来减少/避免多处理器（MP）系统中的内存延迟。 根据一个实施例，在MP环境中将数据从一个处理器传输到另一个处理器的管理被移动到低开销硬件系统中。 低开销硬件系统可以是FIFO（“先进先出”）硬件控制。 每个FIFO可以是真实的或虚拟的。

公开(公告)号：US07447777B1

公开(公告)日：2008-11-04

申请号：US10098957

申请日：2002-02-11

申请人： Ratinder Paul Singh Ahuja ,  Susan Carrie ,  Chien C. Chou ,  Erik De La Iglesia ,  Miguel Gomez ,  Liang Liu ,  Ricky K. Lowe ,  Rahoul Puri ,  Kiet Tran ,  Mark Aaron Wallace ,  Wei Wang ,  Todd E. Wayne ,  Hui Zhang

发明人： Ratinder Paul Singh Ahuja ,  Susan Carrie ,  Chien C. Chou ,  Erik De La Iglesia ,  Miguel Gomez ,  Liang Liu ,  Ricky K. Lowe ,  Rahoul Puri ,  Kiet Tran ,  Mark Aaron Wallace ,  Wei Wang ,  Todd E. Wayne ,  Hui Zhang

IPC分类号： G06F15/16

CPC分类号： H04L12/66 ,  H04L69/40

摘要： Systems and related methods are described for handling one or more resource requests. A protocol engine receives a resource request in accordance with a prescribed protocol, and a classification engine determines a desired class of service for the request. An analysis engine optionally analyzes the request, and, responsive thereto, determines a desired sub-class of service for the request. A policy engine then allocates a resource to the request responsive to one or both of the desired class of service, and the desired sub-class of service.

摘要翻译： 描述了处理一个或多个资源请求的系统和相关方法。 协议引擎根据规定的协议接收资源请求，并且分类引擎确定所请求的期望的服务等级。 分析引擎可选地分析请求，并且响应于此，确定针对请求的期望的服务子类。 然后，策略引擎响应于期望的服务类别和所需的服务子类别中的一个或两个来向请求分配资源。

公开(公告)号：US5016161A

公开(公告)日：1991-05-14

申请号：US413834

申请日：1989-09-28

申请人： James Van Loo ,  Susan Carrie ,  Jerald Evans ,  Jeffrey Spirn

发明人： James Van Loo ,  Susan Carrie ,  Jerald Evans ,  Jeffrey Spirn

IPC分类号： G06F9/50

CPC分类号： G06F9/5011

摘要： The system of the present invention provides for the flow control of commands to devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device. If the valid bits are off or reset and an attempt is made to access at the address, a page fault occurs and the page fault mechanism invokes the page fault handler of the corresponding segment. The page fault mechanism of the MMU and the page fault handler of each segment are then utilized to determine the reason the page fault occurred with respect to a particular process and perform predetermining steps to control the flow of commands to the device.

摘要翻译： 本发明的系统提供对通过系统的存储器管理单元连接的设备的命令的流量控制，并且在多任务计算机系统中特别有用，其中多个进程访问相同的设备。 在本发明的方法和装置中，使用MMU的页面故障机制和每个段中的页面故障处理程序来控制通过MMU连接到系统的设备。 在每个进程的进程地址空间中分配地址以提供通过MMU连接的设备和设备队列的寻址，使得一个设备或一个设备队列被映射到将访问设备的每个进程地址空间的一个段 。 通过进程或操作系统打开/关闭与段中的每个页面相关联的“有效位”，以便控制该设备。 如果有效位关闭或重置，并尝试访问地址，则会发生页面错误，页面错误机制调用相应段的页面错误处理程序。 然后使用MMU的页面故障机制和每个段的页面故障处理程序来确定页面故障相对于特定进程发生的原因，并执行预定步骤来控制到设备的命令流。

公开(公告)号：US09292767B2

公开(公告)日：2016-03-22

申请号：US13344473

申请日：2012-01-05

申请人： Jason Oberg ,  Ken Eguro ,  Victor Tirva ,  Padma Parthasarathy ,  Susan Carrie ,  Alessandro Forin ,  Jonathan Chow

发明人： Jason Oberg ,  Ken Eguro ,  Victor Tirva ,  Padma Parthasarathy ,  Susan Carrie ,  Alessandro Forin ,  Jonathan Chow

IPC分类号： G06F17/00 ,  G06K9/62 ,  G06K9/00 ,  G06N5/04 ,  G06N99/00

CPC分类号： G06K9/00986 ,  G06K9/6282 ,  G06N5/04 ,  G06N99/005

摘要： A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

摘要翻译： 提供了一种用于决策树计算的计算设备。 计算设备可以包括由处理器执行的使用计算设备的存储器的部分的软件程序，该软件程序被配置为从与计算设备相关联的用户输入设备接收用户输入，并且响应于执行决策树 任务。 计算设备还可以包括在硬件中实现的与处理器不同的逻辑电路并且通过通信接口链接到处理器的决策树计算设备。 决策树计算装置可以被配置为从软件程序接收执行与决策树任务相关联的决策树计算的指令，处理指令，并且经由通信接口将结果返回给软件程序。

公开(公告)号：US20150379376A1

公开(公告)日：2015-12-31

申请号：US14318135

申请日：2014-06-27

申请人： Adam James Muff ,  John Allen Tardif ,  Susan Carrie ,  Mark J. Finocchio ,  Kyungsuk David Lee ,  Christopher Douglas Edmonds ,  Randy Crane

发明人： Adam James Muff ,  John Allen Tardif ,  Susan Carrie ,  Mark J. Finocchio ,  Kyungsuk David Lee ,  Christopher Douglas Edmonds ,  Randy Crane

IPC分类号： G06K9/62

CPC分类号： G06K9/6267 ,  G06K9/00973 ,  G06K9/6282

摘要： Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.

摘要翻译： 公开了涉及处理图像像素的实施例。 例如，一个公开的实施例提供了一种用于对包括检索逻辑的像素进行分类的系统; 包括多个像素时隙的像素存储分配，每个像素时隙与像素相关联，其中所述检索逻辑被配置为使所述像素被分配到输入序列中的所述像素时隙中; 流水线处理逻辑被配置为针对每个像素输出与像素相关联的分类信息; 以及调度逻辑，被配置为控制从像素时隙到流水线处理逻辑的调度，其中调度逻辑和流水线处理逻辑被配置为一致地起作用以产生与输出序列不同且独立于的输出序列中的像素的分类信息 输入序列。

公开(公告)号：US5671235A

公开(公告)日：1997-09-23

申请号：US567082

申请日：1995-12-04

申请人： Derek Bosch ,  Susan Carrie

发明人： Derek Bosch ,  Susan Carrie

IPC分类号： G06F11/36 ,  G01R31/28

CPC分类号： G06F11/3656

摘要： In a semiconductor device having a processor for processing digital data and RAM for storing the digital data, an apparatus for accessing the state of the digital data stored in the RAM during system operation for testing purposes. A stall controller is used to stall the processor at a specified point of execution during system operation. The state of the processor at that particular point is shifted out of the registers by using a scan chain and temporarily stored into a buffer. A memory controller then instructs the RAM to write the data of interest into a specific set of test registers. The scan chain is routed through these test registers so that it can serially shift out the data written from the RAM. Thereby, the RAM contents can be accessed with minimal overhead by using the scan chain. Once the data has been shifted out from test registers, the current state of the processor that was stored into the buffer is fed back to the processor. The processor is unstalled and allowed to continue with its normal mode of operation.

摘要翻译： 在具有用于处理数字数据的处理器和用于存储数字数据的RAM的半导体器件中，用于在用于测试目的的系统操作期间访问存储在RAM中的数字数据的状态的装置。 在系统运行期间，停止控制器用于将处理器停在指定的执行点。 处理器在该特定点的状态通过使用扫描链从寄存器中移出并临时存储到缓冲器中。 存储器控制器然后指示RAM将感兴趣的数据写入特定的一组测试寄存器。 扫描链通过这些测试寄存器进行路由，从而可以从RAM中串行移出数据。 因此，可以通过使用扫描链以最小的开销访问RAM内容。 一旦数据从测试寄存器中移出，存储在缓冲器中的处理器的当前状态就被反馈给处理器。 处理器未安装，并允许继续其正常操作模式。