公开(公告)号：US4183089A

公开(公告)日：1980-01-08

申请号：US829013

申请日：1977-08-30

申请人： John W. Daughton ,  Kenneth Gillett ,  Frank M. Nelson

发明人： John W. Daughton ,  Kenneth Gillett ,  Frank M. Nelson

IPC分类号： G03G21/14 ,  G05B19/042 ,  G06F13/00 ,  G06F3/04 ,  G03G15/00 ,  G06F9/06

CPC分类号： G05B19/0423 ,  G03G21/14 ,  G05B2219/2214 ,  G05B2219/25178 ,  G05B2219/25197

摘要： A data communications system for an electrophotographic type reproduction machine or copier. The system includes a programmable master controller with memory and a command byte generator. A plurality of secondary controllers provide input data bytes reflecting the machine status to the master controller and receive command bytes from the master controller for operating the machine components. The secondary controllers are each connected to the master controller such that corresponding data bits of the secondary controller are ORed together to provide simultaneous transmission of input data bytes from the secondary controllers to the master controller while assuring that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

摘要翻译： 一种用于电子照相复制机或复印机的数据通信系统。 该系统包括具有存储器的可编程主控制器和命令字节发生器。 多个次级控制器向主控制器提供反映机器状态的输入数据字节，并且从主控制器接收用于操作机器部件的命令字节。 辅助控制器各自连接到主控制器，使得辅助控制器的相应数据位被OR对齐在一起，以提供从副控制器到主控制器的输入数据字节的同时传输，同时确保同时发送的字节的相应位相互 独家数据。

公开(公告)号：US4137565A

公开(公告)日：1979-01-30

申请号：US758117

申请日：1977-01-10

申请人： George E. Mager ,  Frank M. Nelson ,  Kenneth Gillett ,  Charles P. Holt ,  Edward L. Steiner ,  John W. Daughton ,  Kenton W. Fiske ,  Thomas Criswell ,  Warren L. Hall

发明人： George E. Mager ,  Frank M. Nelson ,  Kenneth Gillett ,  Charles P. Holt ,  Edward L. Steiner ,  John W. Daughton ,  Kenton W. Fiske ,  Thomas Criswell ,  Warren L. Hall

IPC分类号： G03G21/14 ,  G05B19/05 ,  G06F13/12 ,  G06F13/28

CPC分类号： G06F13/285 ,  G05B19/054 ,  G06F13/124 ,  G05B2219/1159 ,  G05B2219/14086 ,  G05B2219/14144 ,  G05B2219/15048 ,  G05B2219/15056

摘要： In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.

摘要翻译： 在诸如具有经由系统总线连接到输入 - 输出处理单元模块的中央处理单元模块的主机的控制器中，作为输入 - 输出处理单元模块的一部分而起作用的直接存储器存取系统 通过直接访问中央处理单元模块中的存储器来提供在主机中刷新和更新控制寄存器的高速装置。 可以对直接存储器存取系统进行编程，以与其正常模式同步刷新主机设备的控制寄存器，同时异步刷新 - 更新控制寄存器，如在周围的电敏周边的检测到的电气干扰的异常模式 控制寄存器，因此需要恢复。 通过直接存储器访问系统的高速数据移动是通过在中央处理单元模块中专用随机存取存储器的一部分进行这种访问来实现的，并且将系统总线从中央处理单元模块的控制转移到直接存储器访问 系统。 这使得能够通过来自专用存储器的固定地址序列访问的数据被直接传送到主机的控制寄存器，而不会产生如果数据由中央处理单元模块中的中央处理器来操纵的时间常数。

公开(公告)号：US4283773A

公开(公告)日：1981-08-11

申请号：US34872

申请日：1979-04-30

申请人： John W. Daughton ,  Kenneth Gillett ,  Frank M. Nelson

发明人： John W. Daughton ,  Kenneth Gillett ,  Frank M. Nelson

IPC分类号： G03G21/14 ,  G05B19/042 ,  G06F13/12 ,  G06F13/22 ,  G06F3/04 ,  G03G15/00 ,  G06F9/06

CPC分类号： G06F13/22 ,  G03G21/14 ,  G05B19/0421 ,  G05B19/0423 ,  G05B2219/2214 ,  G05B2219/25178 ,  G05B2219/25197

摘要： A data communications system having a programmable master controller including memory means and command byte generating means and a plurality of additional controllers providing input data bytes to the master controller and having means for receiving command bytes from the master controller. The additional controllers are each connected to the master controller such that corresponding data bits are ORed together and means are provided for the simultaneous transmission of data bytes from the additional controllers to the master controller such that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

摘要翻译： 一种具有可编程主控制器的数据通信系统，包括存储装置和命令字节产生装置以及向主控制器提供输入数据字节的多个附加控制器，并且具有用于从主控制器接收命令字节的装置。 附加的控制器各自连接到主控制器，使得对应的数据位被OR置于一起，并且提供用于同时从附加控制器向主控制器传输数据字节的装置，使得同时发送的字节的相应位具有互斥数据 其中。

公开(公告)号：US4190350A

公开(公告)日：1980-02-26

申请号：US829015

申请日：1977-08-30

申请人： James J. Donohue ,  Kenneth Gillett ,  Charles P. Holt ,  Andrew T. Ling ,  Richard M. Malinich ,  Frank M. Nelson

发明人： James J. Donohue ,  Kenneth Gillett ,  Charles P. Holt ,  Andrew T. Ling ,  Richard M. Malinich ,  Frank M. Nelson

IPC分类号： G03G15/00 ,  G03G21/14

CPC分类号： G03G15/50

摘要： An electrophotographic reproduction machine for use as a copier/duplicator having a master microprogrammed controller and a plurality of area controllers cooperatively operative to carry out a plurality of machine operation tasks. At least one of the area controllers contains a separate microprogrammed controller for controlling selected tasks and devices in the reproduction machine in synchronism with the operation of other tasks as controlled by the master controller. An optical communication link couples the master and area controllers and serves to isolate the master controller from transients and a direct I/O connection.

摘要翻译： 一种用作具有主微程序控制器和多个区域控制器的复印机/复印机的电子照相再现机，其协作地执行多个机器操作任务。 至少一个区域控制器包含单独的微程序控制器，用于与由主控制器控制的其他任务的操作同步地控制再现机器中的所选任务和设备。 光通信链路耦合主控区域和区域控制器，用于隔离主控制器与瞬态和直接I / O连接。

公开(公告)号：US5686915A

公开(公告)日：1997-11-11

申请号：US579113

申请日：1995-12-27

申请人： Frank M. Nelson ,  Thanh D. Truong ,  Vinod Kadakia

发明人： Frank M. Nelson ,  Thanh D. Truong ,  Vinod Kadakia

IPC分类号： G06T9/00 ,  H03M7/42 ,  H03M7/40

CPC分类号： G06T9/005 ,  H03M7/425

摘要： A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

摘要翻译： 以每个时钟周期的速率对霍夫曼编码的字进行解码的方法。 编码的字形成两个位串，一个用于奇数编号，一个用于偶数编号，并且使用两个并行解码器，每个第一个时钟周期期间以多个编码位移位，并转换霍夫曼 代码到第二个时钟周期的数据。 两个并行解码器被定时，使得一个解码器的移位周期与另一个解码器的转换周期同时发生。 最后，解码的数据字的两个流被组合为一个流。 结果是每个时钟周期的一个输出数据字。

公开(公告)号：US4141068A

公开(公告)日：1979-02-20

申请号：US780875

申请日：1977-03-24

申请人： George E. Mager ,  Frank M. Nelson ,  Steven L. Reid ,  Philip Richardson ,  Vernon E. Rochat ,  Donald S. Post

发明人： George E. Mager ,  Frank M. Nelson ,  Steven L. Reid ,  Philip Richardson ,  Vernon E. Rochat ,  Donald S. Post

IPC分类号： G06F12/06 ,  G06F9/26 ,  G06F9/445 ,  G06F13/00

CPC分类号： G06F8/66 ,  G06F12/0638

摘要： An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

摘要翻译： 分级的辅助ROM存储器系统，用于提供附加的只读存储器控制程序存储要求的过多或替代提供在基于微处理器的中央处理单元模块上的预定ROM存储器的可能性，以及只读 利用可编程只读存储器来加快对ROM位模式的改变的实现/安装的存​​储器改变能力。 可变的PROM存储器包括批量PROM存储器，其包括与现有的板上ROM存储器相互排斥的第一PROM集合，用于可寻址地分支到代码扩展和/或在线代码插入，和/或相互间的第二PROM集合 包括存在的板载和即时ROM存储器，用于可解码地寻址大规模代码覆盖。 另外，可改变的PROM存储器包括补丁PROM，用于通过多级解码将小规模代码叠加到板上以及用于单列直插位模式改变的偶然ROM存储器中。 涉及存储器请求的相互关联的存储器请求被提供给存储器优先级的预定层级以进行解析，这些存储器请求涉及由超过一个存储器类别识别的地址的存储器请求。 辅助ROM存储器系统的每个枚举的存储器类别可以操作以使其总体增加或减少，而不使上述寻址层次化。

公开(公告)号：US4144550A

公开(公告)日：1979-03-13

申请号：US829014

申请日：1977-08-30

申请人： James M. Donohue ,  Andrew T. Ling ,  Richard M. Malinich ,  Frank M. Nelson

发明人： James M. Donohue ,  Andrew T. Ling ,  Richard M. Malinich ,  Frank M. Nelson

IPC分类号： G03G15/00 ,  G05B19/042 ,  H04B9/00

CPC分类号： G03G15/50 ,  G05B19/0421 ,  G05B19/0423 ,  G05B2219/25197

摘要： A reproduction machine having a plurality of operating stations and a plurality of devices for controlling operational tasks of said operating stations comprising a master controller having an arithmetic and logic unit for controlling the devices in accordance with sensed operational parameters and a stored operation program and interface means connected in a communication path between the master controller and the devices. The interface means comprises a fiber-optic communication path for isolating the master controller from electrical noise and transients of the devices.

摘要翻译： 一种具有多个操作站和多个用于控制所述操作站的操作任务的设备的再现机器，包括具有用于根据感测到的操作参数来控制设备的算术和逻辑单元的主控制器，以及存储的操作程序和接口装置 连接在主控制器和设备之间的通信路径中。 接口装置包括用于将主控制器与电气噪声和设备的瞬变隔离的光纤通信路径。

公开(公告)号：US4131944A

公开(公告)日：1978-12-26

申请号：US758892

申请日：1977-01-12

申请人： George E. Mager ,  Frank M. Nelson ,  Warren L. Hall

发明人： George E. Mager ,  Frank M. Nelson ,  Warren L. Hall

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/285

摘要： In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.

摘要翻译： 在具有通过包括访问数据存储器的数据，地址和控制线的系统总线耦合的中央处理器的控制模块中，包括通过系统总线耦合的直接访问装置，以请求中央处理器的保持并且直接确认 通过系统总线访问数据存储器，以指导主机的控制寄存器。 还包括连接到中央处理器的连接元件，用于从用于保持请求的直接访问装置接收系统总线上的控制信号，以及从中央处理器传输用于确认的系统总线上的第一和第二控制信号，以及 定时协议单元，用于监控在系统总线上传输的数据，地址和控制信号。 定时协议单元包括通过系统总线耦合到中央处理器的地址控制器，用于在从系统单元接收到系统总线上的第一确认信号时，使地址信号消失，以及通过系统总线耦合到中央处理器的数据控制 用于在从系统元件接收系统总线上的第二应答信号时双向禁用数据信号。