公开(公告)号：US06725339B2

公开(公告)日：2004-04-20

申请号：US10061816

申请日：2002-01-31

申请人： John Wai Cheong Fu ,  Dean Ahmad Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer ,  Jeng-Jye Shaw

发明人： John Wai Cheong Fu ,  Dean Ahmad Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer ,  Jeng-Jye Shaw

IPC分类号： G06F1200

CPC分类号： G06F12/0855

摘要： A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

摘要翻译： 提供了一种从存储器请求数据的方法。 该方法包括向存储器的数据请求端口发出多个数据请求。 多个数据请求包括至少两个有序数据请求。 所述方法包括确定所述有序数据请求中的较早的一个是否对应于所述存储器中的未命中，以及响应于对应于未命中的所述有序数据请求中的较早的一个，将所述有序数据请求中的后一个转换为预取 记忆。 一种装置包括具有用于接收数据请求的至少一个流水线端口的存储器。 该端口适于确定数据请求中较早订购的数据请求是否对应于存储器中的未命中。 响应于确定早期有序的数据请求对应于存储器中的未命中，端口将稍后排序的数据请求转换为预取。

公开(公告)号：US06381678B2

公开(公告)日：2002-04-30

申请号：US09183519

申请日：1998-10-30

申请人： John Wai Cheong Fu ,  Dean Ahmad Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer ,  Jeng-Jye Shaw

发明人： John Wai Cheong Fu ,  Dean Ahmad Mulla ,  Gregory S. Mathews ,  Stuart E. Sailer ,  Jeng-Jye Shaw

IPC分类号： G06F1200

CPC分类号： G06F12/0855

摘要： A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

摘要翻译： 提供了一种从存储器请求数据的方法。 该方法包括向存储器的数据请求端口发出多个数据请求。 多个数据请求包括至少两个有序数据请求。 所述方法包括确定所述有序数据请求中的较早的一个是否对应于所述存储器中的未命中，以及响应于对应于未命中的所述有序数据请求中的较早的一个，将所述有序数据请求中的后一个转换为预取 记忆。 一种装置包括具有用于接收数据请求的至少一个流水线端口的存储器。 该端口适于确定数据请求中较早订购的数据请求是否对应于存储器中的未命中。 响应于确定早期有序的数据请求对应于存储器中的未命中，端口将稍后排序的数据请求转换为预取。

公开(公告)号：US06226763B1

公开(公告)日：2001-05-01

申请号：US09126029

申请日：1998-07-29

申请人： John Wai Cheong Fu ,  Dean Ahmad Mulla

发明人： John Wai Cheong Fu ,  Dean Ahmad Mulla

IPC分类号： H02H305

CPC分类号： G06F11/1064 ,  G06F12/0802

摘要： A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection.

摘要翻译： 一种用于执行高速缓存访​​问的方法和装置。 比较器耦合到高速缓存和查找奇偶校验位线以执行错误检测。

公开(公告)号：US6134636A

公开(公告)日：2000-10-17

申请号：US151740

申请日：1998-09-11

申请人： Gregory Scott Mathews ,  John Wai Cheong Fu ,  Dean Ahmad Mulla

发明人： Gregory Scott Mathews ,  John Wai Cheong Fu ,  Dean Ahmad Mulla

IPC分类号： G06F12/12 ,  G06F12/00 ,  G06F12/14

CPC分类号： G06F12/124 ,  G06F12/126 ,  G06F12/128

摘要： A method and apparatus for storing, locking, and unlocking data in a memory array. The memory array includes a first line to store a first type of data while the first line is unlocked during a first period of time and to store a second type of data while the first line is locked during a subsequent second period of time. The memory array further includes a second line to store the second type of data while the second line is locked during the first period of time and to store the first type of data while the second line is unlocked during the second period of time.

摘要翻译： 一种用于在存储器阵列中存储，锁定和解锁数据的方法和装置。 存储器阵列包括用于存储第一类型的数据的第一行，而第一行在第一时间段期间被解锁并且在第一行在随后的第二时间段期间被锁定时存储第二类型的数据。 存储器阵列还包括用于存储第二类型的数据的第二行，而在第一时间段期间第二行被锁定并且在第二时间段期间第二行被解锁时存储第一类型的数据。

公开(公告)号：US07680990B2

公开(公告)日：2010-03-16

申请号：US10449442

申请日：2003-05-30

申请人： Donald C. Soltis ,  Dale C. Morris ,  Dean Ahmad Mulla ,  Achmed Rumi Zahir ,  Amy Lynn O'Donnell ,  Allan Douglas Knies

发明人： Donald C. Soltis ,  Dale C. Morris ,  Dean Ahmad Mulla ,  Achmed Rumi Zahir ,  Amy Lynn O'Donnell ,  Allan Douglas Knies

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30112 ,  G06F9/3834

摘要： Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.

摘要翻译： 在64位系统中提供原子十六字节的存储器访问，其中八个字节存储在64位通用寄存器中，八个字节存储在64位专用寄存器中。 一个16字节的加载指令将低8个字节传送到明确指定的通用寄存器，而高8个字节传送到专用寄存器。 同样，一个16字节的存储指令从通用寄存器和专用寄存器传送数据。 还提供了一个8字节比较调节16字节交换信号量指令，可用于加速使用多个处理器同时读取和更新大型数据库的算法。