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1.发明授权Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase 失效完全互补的MOS存储单元，在编程和擦除期间通过NMOS和PMOS晶体管隧穿
公开(公告)号：US5594687A
公开(公告)日：1997-01-14
申请号：US447991
申请日：1995-05-23
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a PAL device.
摘要翻译： 电路添加到CMOS存储器单元中，配置为能够通过其PMOS和NMOS晶体管进行隧穿，该电路可防止编程期间的漏电流。 该电路包括用于将CMOS单元的NMOS晶体管的源极连接到Vss的单独的NMOS通孔。 在通过PMOS晶体管的编程期间，NMOS栅极的栅极被控制为关闭NMOS晶体管，以防止Vss线上的电流损耗。 NMOS栅极进一步提供用于启用或禁用NMOS晶体管的装置，其使得CMOS单元可用作PAL器件的阵列单元。
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2.发明授权CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors 失效在通过NMOS和PMOS晶体管编程和擦除期间具有隧穿的CMOS存储器单元以及分离NMOS和PMOS晶体管的通过栅极
公开(公告)号：US5646901A
公开(公告)日：1997-07-08
申请号：US625403
申请日：1996-03-26
IPC分类号： G11C16/04 , H01L27/115 , G11C7/00
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.
摘要翻译： 一种装置和方法，该装置包括分离CMOS存储器单元的NMOS和NMOS晶体管的NMOS栅极，配置用于在编程和擦除期间通过NMOS和PMOS晶体管进行隧穿。 附加的NMOS通道栅极使CMOS存储器单元可以用作可编程逻辑器件（PLD）中的存储器单元。 该方法包括编程和擦除CMOS存储器单元以防止电流泄漏的步骤。 这些步骤包括在编程和擦除期间将特定电压施加到NMOS和PMOS晶体管的源，而不是将源浮置。 可以在编程或擦除期间施加这样的电压，而不需要在单独的CMOS单元的PMOS或NMOS晶体管的源极上连接附加的通路栅极，或者如所描述的装置中那样在PMOS和NMOS的漏极之间提供附加的通过栅极。
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3.发明授权CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase 失效具有NMOS和PMOS晶体管的栅极氧化物的CMOS存储单元作为用于编程和擦除的隧道窗口
公开(公告)号：US5596524A
公开(公告)日：1997-01-21
申请号：US427117
申请日：1995-04-21
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： A CMOS memory cell including a PMOS transistor and an NMOS transistor having a common floating gate with a gate oxide region of both the NMOS and PMOS transistors providing a tunneling window for program and erase. The PMOS and NMOS transistors of the CMOS memory cell are biased so that only the PMOS transistor is utilized during programming and only the NMOS transistor is utilized during erase to prevent depletion of the substrate beneath the tunneling oxide regions. The CMOS memory cell further includes a separate PMOS pass transistor for supplying a program voltage to the source of the PMOS transistor underlying the common floating gate, so that an NMOS threshold does not have to be added to the program voltage.
摘要翻译： 包括PMOS晶体管和NMOS晶体管的CMOS存储单元，其具有公共浮置栅极，NMOS晶体管和PMOS晶体管的栅极氧化物区域提供用于编程和擦除的隧道窗口。 CMOS存储单元的PMOS晶体管和NMOS晶体管被偏置，使得在编程期间仅使用PMOS晶体管，并且在擦除期间仅使用NMOS晶体管以防止在隧穿氧化物区域下面的衬底的耗尽。 CMOS存储单元还包括用于向编程电压下面的PMOS晶体管的源极提供编程电压的单独PMOS通道晶体管，从而不必将NMOS阈值加到编程电压上。
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公开(公告)号：US07028281B1
公开(公告)日：2006-04-11
申请号：US10194771
申请日：2002-07-12
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , G06F17/5054 , H01L2924/0002 , H03K19/17728 , H03K19/17784 , H01L2924/00
摘要： Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.
摘要翻译： 现场可编程门阵列（FPGA）可以根据本公开进行结构化以具有寄存器密集型架构，其针对逻辑块内的多个功能产生查找表（例如，4输入，基本LUT）中的每一个提供寄存器密集型结构， 多个块内可访问寄存器。 可以提供寄存器馈送多路复用器装置，用于允许多个寄存器中的每一个等效地捕获并存储由多个寄存器的相应的基本LUT输出的结果信号。 可以为每个基本LUT提供可登记的主和辅助馈通，使得LUT的本地采集的输入信号可以被馈送到相应的块内寄存器用于寄存器恢复目的，而不会完全消耗（浪费）查找资源 的相关的基本LUT。 可以进一步提供多级输入开关矩阵（ISM），用于从相邻的块互连线（AIL）和/或块内连接线（例如，FB）到基本LUT的采集和路由输入信号，并且 /或其各自的可注册馈通。 公开了利用许多块内寄存器和/或可注册馈通和/或多级ISM的技术来通过适当地配置这种寄存器密集型FPGA来有效地实现各种电路设计。
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5.发明授权Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility 有权具有CMOS驱动器门电流控制的输入缓冲器，可实现PCL，GTL或PECL的兼容性公开(公告)号：US06870391B1
公开(公告)日：2005-03-22
申请号：US10146769
申请日：2002-05-16
IPC分类号： G06F7/38 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/018585
摘要： An input/output buffer is provided which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a first pair of CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. Switching circuitry includes transistors which drive gates of the CMOS transistors to set the output (OUT) with a current level and a voltage level depending on a desired output drive current and voltage.
摘要翻译： 提供了一种输入/输出缓冲器，可用于使集成电路选择性地兼容多种接口类型之一，如PCI，GTL，PECL，ECL和SSTI。 输入缓冲器部分包括第一对CMOS晶体管，用于驱动类似于CMOS逻辑的VSS和VDD电压之间的输出（OUT）。 开关电路包括驱动CMOS晶体管的栅极的晶体管，以根据期望的输出驱动电流和电压将电流电平和电压电平设置为输出（OUT）。
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公开(公告)号：US06798244B1
公开(公告)日：2004-09-28
申请号：US10151753
申请日：2002-05-16
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K17/163
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The input buffer includes switching circuitry driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The switching circuitry includes components to prevent damage to low voltage transistors used in the output buffer should the output pad (PAD) voltage exceed VDD, or should charge buildup occur on the common well of PMOS transistors used in the output buffer exceed VDD.
摘要翻译： 输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。 输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。 输入缓冲器包括驱动多个CMOS缓冲晶体管的栅极的开关电路，以提供足够的电流用于快速开关，并且在切换之后限制电流以准备随后的输出转换。 如果输出缓冲器（PAD）电压超过VDD，或者在输出缓冲器中使用的PMOS晶体管的公共阱上的电荷积累超过VDD，则开关电路包括防止损坏输出缓冲器中使用的低压晶体管的组件。
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7.发明授权Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility 失效输出缓冲器，具有来自输入缓冲器的反馈，提供可选择的PCL，GTL或PECL兼容性公开(公告)号：US06657458B1
公开(公告)日：2003-12-02
申请号：US10146826
申请日：2002-05-16
IPC分类号： H03K19177
CPC分类号： H03K19/018585
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The signal from the PAD is further fed back through the input buffer portion which programmably set to operate in a PCI, PECL or GTL mode to control a node (INB). The node (INB) is used to control power switches driving the gates of CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. Pull-up and pull-down reference circuits provide references VRFPU, VRFPPU, VRFPD and VRFPPD to control the current of the output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.
摘要翻译： 输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。 输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。 来自PAD的信号通过可编程设置为以PCI，PECL或GTL模式操作以控制节点（INB）的输入缓冲器部分进一步反馈。 节点（INB）用于控制驱动CMOS缓冲晶体管的栅极的电源开关，以提供足够的电流用于快速开关，并在切换后限制电流以准备后续的输出转换。 上拉和下拉参考电路提供参考VRFPU，VRFPPU，VRFPD和VRFPPD，以在输出转换期间控制输出电流，同时在转换后以最小的电流水平将输出电压电平保持在所需电压。
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8.发明授权FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。
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9.发明授权Operational amplifier with CMOS transistors made using 2.5 volt process transistors 有权具有采用2.5伏过程晶体管的CMOS晶体管的运算放大器公开(公告)号：US06175266B1
公开(公告)日：2001-01-16
申请号：US09207558
申请日：1998-12-08
IPC分类号： G05F302
CPC分类号： G05F1/575
摘要： A power converter includes an opamp (FIG. 5) with CMOS transistors made using 2.5 volt process technology which tolerates a maximum gate voltage of 2.7 volts. The opamp is driven by a pin supply voltage (NV3EXT) with a maximum value of 3.6 volts. The connection of the transistors of the opamp (FIG. 5) provides a maximum gate to source, and gate to drain voltage on each transistor which is less than 2.7 volts when NV3EXT is at 3.6 volts. Further, the output (OUT) of the opamp (FIG. 5) is referenced to ground, rather than NV3EXT to prevent fluctuations in the input voltage offset relative to NV3EXT, and minimize variations in the output voltage margin of the power converter.
摘要翻译： 功率转换器包括具有使用2.5伏工艺技术制造的CMOS晶体管的运算放大器（图5），其允许2.7V的最大栅极电压。 运算放大器由最大值为3.6伏特的引脚电源电压（NV3EXT）驱动。 当NV3EXT为3.6伏时，运算放大器（图5）的晶体管的连接提供了每个晶体管上的最大栅极至源极以及小于2.7伏特的栅极至漏极电压。 此外，运算放大器（图5）的输出（OUT）参考地，而不是NV3EXT，以防止相对于NV3EXT的输入电压偏移的波动，并使功率转换器的输出电压余量的变化最小化。
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10.发明授权High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process 有权高压开关用于提供高于2.5伏特的电压，使用2.5伏工艺制造的晶体管公开(公告)号：US06169432A
公开(公告)日：2001-01-02
申请号：US09188778
申请日：1998-11-09
IPC分类号： H03B100
CPC分类号： H03K17/102
摘要： A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts. A PMOS transistor (366) has a gate tied to the drain of cascode (361) and provides Vcc to the switch output (n10). A PMOS transistor (368) has a gate tied to the gate of transistor 365 and supplies 4.5 volts to the switch output (n10). In operation, the switch (350) functions to selectively transition its output (n10) between Vcc and 4.5 volts without applying greater than 2.7 volts from the gate to source, gate to drain, or source to drain of any of its transistors.
摘要翻译： 提供由2.5伏过程晶体管组成的电压开关，其容许最大的栅极到源极，栅极到漏极或漏极到源极电压为2.7伏特。 电压开关晶体管被布置成在诸如2.5伏特的电压和诸如4.5伏特的高得多的电压之间切换。 在一个实施例（350）中，电压开关包括提供给NMOS共源共栅连接晶体管（360）的源极的输入端。 反相器（354）将NMOS共源共栅（360）的源极连接到另一个NMOS共源共栅（361）的源极。 共源共栅晶体管被定义为连接，使得其通过在栅极电压固定的情况下改变源极电压来导通和关断，而不是改变栅极电压。 级联（360,361）的栅极连接到Vcc（2.5伏特）。 PMOS级联晶体管（362）和（363）将各自的共源共栅晶体管（360）和（361）的漏极连接到PMOS晶体管（364）和（365）。 PMOS晶体管（364）和（365）具有连接到4.5伏特的源极。 PMOS晶体管（366）具有连接到共源共栅（361）的漏极的栅极，并向开关输出（n10）提供Vcc。 PMOS晶体管（368）具有连接到晶体管365的栅极的栅极，并向开关输出（n10）提供4.5伏特。 在操作中，开关（350）用于选择性地将其输出（n10）在Vcc和4.5V之间转变，而不施加大于2.7伏的栅极至源极，栅极至漏极或其任何晶体管的源极到漏极。
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