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公开(公告)号：US07028281B1
公开(公告)日：2006-04-11
申请号：US10194771
申请日：2002-07-12
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , G06F17/5054 , H01L2924/0002 , H03K19/17728 , H03K19/17784 , H01L2924/00
摘要： Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.
摘要翻译： 现场可编程门阵列（FPGA）可以根据本公开进行结构化以具有寄存器密集型架构，其针对逻辑块内的多个功能产生查找表（例如，4输入，基本LUT）中的每一个提供寄存器密集型结构， 多个块内可访问寄存器。 可以提供寄存器馈送多路复用器装置，用于允许多个寄存器中的每一个等效地捕获并存储由多个寄存器的相应的基本LUT输出的结果信号。 可以为每个基本LUT提供可登记的主和辅助馈通，使得LUT的本地采集的输入信号可以被馈送到相应的块内寄存器用于寄存器恢复目的，而不会完全消耗（浪费）查找资源 的相关的基本LUT。 可以进一步提供多级输入开关矩阵（ISM），用于从相邻的块互连线（AIL）和/或块内连接线（例如，FB）到基本LUT的采集和路由输入信号，并且 /或其各自的可注册馈通。 公开了利用许多块内寄存器和/或可注册馈通和/或多级ISM的技术来通过适当地配置这种寄存器密集型FPGA来有效地实现各种电路设计。
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2.发明授权FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。
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3.发明授权Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。 每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。
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4.发明授权Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan 有权多端口SRAM单元阵列具有多个写入路径，包括用于通过可寻址端口进行写入和通过串行边界扫描
公开(公告)号：US6097664A
公开(公告)日：2000-08-01
申请号：US235356
申请日：1999-01-21
CPC分类号： G11C8/16
摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.
摘要翻译： 串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。 响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。
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公开(公告)号：US6097212A
公开(公告)日：2000-08-01
申请号：US948306
申请日：1997-10-09
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.
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6.发明授权Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices 失效用于非常高密度复杂可编程逻辑器件的多层分层高速开关矩阵结构
公开(公告)号：US5818254A
公开(公告)日：1998-10-06
申请号：US459230
申请日：1995-06-02
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix, a segment switch matrix and a block switch matrix. The block switch matrix provides a high speed signal path for signals within a programmable logic block. The segment switch matrix provides a high speed means of communication for signals within a segment, while the global switch matrix provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.
摘要翻译： 非常高密度可编程逻辑器件（CPLD）中的分层开关矩阵互连了CPLD中的多个可编程逻辑块。 通过分层交换矩阵提供了一个新的功能级别与高速度。 分层交换矩阵包括三个层次，全局交换矩阵，分段交换矩阵和块交换矩阵。 块开关矩阵为可编程逻辑块内的信号提供高速信号路径。 分段开关矩阵为段内的信号提供高速通信装置，而全局开关矩阵为段之间的通信提供高速路径。 本发明的分层交换矩阵为通过分层交换矩阵路由的每组信号提供固定的，路径独立的，均匀的，可预测的和确定性的时间延迟。
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7.发明授权Programmable optimized-distribution logic allocator for a high-density complex PLD 失效用于高密度复合PLD的可编程优化分配逻辑分配器公开(公告)号：US06753696B1
公开(公告)日：2004-06-22
申请号：US10338619
申请日：2003-01-08
IPC分类号： H03K19173
CPC分类号： H03K19/177 , H03K19/1737 , H03K19/17704
摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.
摘要翻译： 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。 每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。
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8.发明授权Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources 有权用于配置具有可变粒度块和共享逻辑的FPGA的方法，用于将结果输出的对称路由提供给不同方向和可三态互连资源公开(公告)号：US06204686B1
公开(公告)日：2001-03-20
申请号：US09216662
申请日：1998-12-16
IPC分类号： G06F738
CPC分类号： H03K19/17756 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.
摘要翻译： 可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。 多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。 路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。
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9.发明授权Efficient interconnect network for use in FPGA device having variable grain architecture 有权高效互连网络，用于具有可变粒度架构的FPGA器件
公开(公告)号：US06163168A
公开(公告)日：2000-12-19
申请号：US208203
申请日：1998-12-09
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.
摘要翻译： 逻辑阵列器件具有多个互连资源的阵列，包括多个线路和多个开关盒区域，多个可变格栅块（VGB）的阵列散布在多个互连资源的阵列内。 多个互连资源的阵列不规则地包括单个长度或更短的线，并且多个互连资源的阵列不规则地包括通过单个长度或更短的距离彼此间隔开的开关盒区域。 单个长度对应于覆盖大约一个VGB的连续距离的横越。
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10.发明授权Tileable and compact layout for super variable grain blocks within FPGA device 有权FPGA器件内的超可变晶粒块的平铺紧凑布局
公开(公告)号：US06154051A
公开(公告)日：2000-11-28
申请号：US187689
申请日：1998-11-05
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
IPC分类号： H01L27/02 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/0207 , H03K19/1778 , H03K19/17796
摘要： A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.
摘要翻译： 为逻辑阵列器件提供了可瓦片结构。 可瓦片结构具有逻辑块集合的逻辑对称布置，用于逻辑块集合的公共控制部分，周围互连线以及互连线的交叉处的交换区域。
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