公开(公告)号：US20130234288A1

公开(公告)日：2013-09-12

申请号：US13614893

申请日：2012-09-13

申请人： Sung Mo GU ,  Moon Hyung CHO ,  Young Sang KIM ,  Jong Bum PARK

发明人： Sung Mo GU ,  Moon Hyung CHO ,  Young Sang KIM ,  Jong Bum PARK

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/60

摘要： A method for manufacturing a MIM capacitor trench structure includes forming a lower metal film on an inter-metal dielectric; forming a first inter-metal dielectric on the lower metal film; forming a first trench; sequentially forming a dielectric film and a first barrier metal film along the bottom surface and sidewalls of the first trench; and filling the first trench with a conductive material to form a first upper metal film. Further, the method includes forming a second inter-metal dielectric on the first upper metal film; forming a second trench; forming a via hole in a via hole region of the second inter-metal dielectric; forming a second barrier metal film along the bottom surface and sidewalls of the second trench; and filling the via hole and the second trench with the conductive material to form a via contact and a second upper metal film.

摘要翻译： 一种用于制造MIM电容器沟槽结构的方法，包括在金属间电介质上形成下金属膜; 在下金属膜上形成第一金属间电介质; 形成第一沟槽; 沿着第一沟槽的底表面和侧壁依次形成电介质膜和第一阻挡金属膜; 以及用导电材料填充所述第一沟槽以形成第一上金属膜。 此外，该方法包括在第一上金属膜上形成第二金属间电介质; 形成第二沟槽; 在所述第二金属间电介质的通孔区域中形成通孔; 沿着第二沟槽的底表面和侧壁形成第二阻挡金属膜; 以及用所述导电材料填充所述通孔和所述第二沟槽，以形成通孔接触和第二上部金属膜。

公开(公告)号：US20110159676A1

公开(公告)日：2011-06-30

申请号：US12978832

申请日：2010-12-27

申请人： Jong Bum PARK ,  Chun Ho KANG ,  Young Seung KIM

发明人： Jong Bum PARK ,  Chun Ho KANG ,  Young Seung KIM

IPC分类号： H01L21/30 ,  G06F19/00

CPC分类号： H01L27/10888 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/28525 ,  H01L23/485 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

摘要翻译： 导电层可以通过将硅衬底加载到内部温度处于约250℃至约300℃范围内的负载温度的室中而在半导体衬底上制造，从而增加室的内部温度 从加载温度到加工温度，并且通过将硅源气体和杂质源气体提供到室中，其中腔室可以是例如在硅衬底上顺序地堆叠单晶硅层和多晶硅层 ，CVD室或LPCVD室。

公开(公告)号：US20090230511A1

公开(公告)日：2009-09-17

申请号：US12471917

申请日：2009-05-26

申请人： Jong Bum PARK

发明人： Jong Bum PARK

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L21/0228 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31691 ,  H01L28/55

摘要： A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the storage node contact. Also, a dielectric film comprised of a composite dielectric of a SrTiO3 film and an anti-crystallization film is formed on the storage electrode. Finally, a plate electrode is formed on the dielectric film.

摘要翻译： 用于形成半导体器件的电容器的方法确保充电容量并改善漏电流特性。 在电容器形成方法中，首先制备形成有存储节点接触的半导体衬底。 接下来，形成存储电极，使得存储电极连接到存储节点触点。 此外，在存储电极上形成由SrTiO 3膜的复合电介质和抗结晶膜构成的电介质膜。 最后，在电介质膜上形成平板电极。