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    Precharging apparatus and method in a semiconductor memory device
    3.
    发明授权
    Precharging apparatus and method in a semiconductor memory device 失效
    一种半导体存储装置中的预充电装置和方法

    公开(公告)号：US06256245B1

    公开(公告)日：2001-07-03

    申请号：US09634058

    申请日：2000-08-09

    申请人： Jin Seok Kwak

    发明人： Jin Seok Kwak

    IPC分类号： G11C700

    CPC分类号： G11C7/1048 ,  G11C7/12

    摘要： A precharging apparatus and method is applicable to a semiconductor device having a stack bank-type structure. The device comprises a plurality of memory cell array banks, a plurality of memory cell array blocks of each memory cell array bank comprising a predetermined number of partial blocks connected respectively to the predetermined number of groups of the plurality of partial local data input/output line pairs, in turn connected respectively to the predetermined number of groups of the plurality of global data input/output line pairs, a plurality of switching means which are connected respectively between the predetermined number of groups of the plurality of partial local data input/output line pairs and which are used to connect the predetermined number of groups of the plurality of partial local data input/output line pairs in response to a precharge signal, and a predetermined number of precharge means to precharge the predetermined number of groups of the plurality of partial local data input/output line pairs of each memory cell array block in response to the precharge signal. In this manner, the overall chip size can be reduced by reducing the number of transistors used during a precharge operation.

    摘要翻译： 预充电装置和方法可应用于具有堆叠组型结构的半导体器件。 该设备包括多个存储单元阵列组，每个存储单元阵列组的多个存储单元阵列块包括分别连接到多个局部本地数据输入/输出线中的预定数量的组的预定数量的部分块 成对又分别连接到多个全局数据输入/输出线对中的预定​​数量的组，多个切换装置分别连接在多个局部本地数据输入/输出线的预定数量的组之间 并且用于响应于预充电信号连接多个部分局部数据输入/输出线对中的预定​​数量的组，以及预定数量的预充电装置，用于对多个部分局部数据输入/输出线对中的预定​​数量的组进行预充电 响应于预充电信号，每个存储单元阵列块的本地数据输入/输出线对。 以这种方式，通过减少在预充电操作期间使用的晶体管的数量，可以减小总体芯片尺寸。

    Redundancy circuit and redundancy method for semiconductor memory device
    4.
    发明授权
    Redundancy circuit and redundancy method for semiconductor memory device 有权
    半导体存储器件的冗余电路和冗余方法

    公开(公告)号：US06320801B1

    公开(公告)日：2001-11-20

    申请号：US09643323

    申请日：2000-08-21

    申请人： Jin Seok Kwak

    发明人： Jin Seok Kwak

    IPC分类号： G11C2900

    CPC分类号： G11C29/808 ,  G11C29/846

    摘要： A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.

    摘要翻译： 半导体存储器件的冗余电路包括产生模式信号的模式设置电路，响应于模式信号产生选择信号的输入选择电路，以及响应于模式选择信号产生解码信号的解码电路 。 冗余模式信号包括存储体冗余模式信号，阵列冗余模式信号和列地址组冗余模式信号。 选择信号以行冗余模式识别存储体，阵列冗余模式中的阵列，列地址组冗余模式中的列地址组。 解码信号开始替换与半导体存储器件中的有缺陷的存储器单元相关联的数据I / O线对。 冗余方法包括：产生冗余模式信号; 响应冗余模式信号产生选择信号; 并产生解码信号。

    Semiconductor memory device and redundancy method thereof
    5.
    发明授权
    Semiconductor memory device and redundancy method thereof 失效
    半导体存储器件及其冗余方法

    公开(公告)号：US06590814B1

    公开(公告)日：2003-07-08

    申请号：US09717889

    申请日：2000-11-20

    申请人： Jin Seok Kwak

    发明人： Jin Seok Kwak

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C29/848

    摘要： In a semiconductor memory device that includes memory cell array banks, memory cell array blocks in each memory cell array bank, partial blocks in each memory cell array block, data input/output line pairs connected to the partial blocks, and a predetermined number of redundant partial blocks connected to a predetermined number of redundant data input/output line pairs, the semiconductor memory device further includes an address setting circuit to set a redundant control signal and a defect address of each of the memory cell array blocks, decoder and shifting control signal generating circuits to generate shifting control signals to control shifting of the data input/output line pairs and the predetermined number of redundant data input/output line pairs by decoding the redundant control signal and the defective address, and switching circuits for routing data through data input/output line pairs adjacent to a corresponding data input/output line pairs in response to each of the shifting control signals. Therefore, the semiconductor memory device can generate the shifting control signals dynamically to column cycle and can construct a redundancy circuit with a small number of fuses.

    摘要翻译： 在包括存储单元阵列组的半导体存储器件中，每个存储单元阵列组中的存储单元阵列块，每个存储单元阵列块中的部分块，连接到该部分块的数据输入/输出线对以及预定数量的冗余 连接到预定数量的冗余数据输入/输出线对的部分块，所述半导体存储器件还包括地址设置电路，用于设置每个存储单元阵列块的冗余控制信号和缺陷地址，解码器和移位控制信号 生成电路以通过解码冗余控制信号和缺陷地址来产生移位控制信号以控制数据输入/输出线对和预定数量的冗余数据输入/输出线对的移位，以及用于通过数据输入路由数据的切换电路 /输出线对对应于相应的数据输入/输出线对，以响应每个移位 ng控制信号。 因此，半导体存储器件可以动态地产生移位控制信号到列周期，并且可以构造具有少量熔丝的冗余电路。