公开(公告)号：US06522597B2

公开(公告)日：2003-02-18

申请号：US09947392

申请日：2001-09-07

申请人： Jong Hyun Choi ,  Sang Seok Kang ,  Jae Hoon Joo

发明人： Jong Hyun Choi ,  Sang Seok Kang ,  Jae Hoon Joo

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

摘要： State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

公开(公告)号：US08228736B2

公开(公告)日：2012-07-24

申请号：US12591976

申请日：2009-12-07

申请人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C16/04

CPC分类号： G06F1/206 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

摘要： A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

摘要翻译： 移动片上系统（SoC）包括微处理器和被配置为控制第一存储器的刷新的第一存储器控制器。 温度传感器检测第一存储器中的温度。 当从温度传感器接收到的第一温度信息指示检测到的温度偏离预定温度范围时，第一存储器控制器控制第一存储器以便不进行自刷新。 当从温度传感器接收到的第二温度信息指示检测到的温度处于预定温度范围时，第一存储器控制器向第一存储器输出自刷新命令。

公开(公告)号：US20100142291A1

公开(公告)日：2010-06-10

申请号：US12591976

申请日：2009-12-07

申请人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C7/00 ,  G06F1/04

CPC分类号： G06F1/206 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

摘要： A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

摘要翻译： 移动片上系统（SoC）包括微处理器和被配置为控制第一存储器的刷新的第一存储器控制器。 温度传感器检测第一存储器中的温度。 当从温度传感器接收到的第一温度信息指示检测到的温度偏离预定温度范围时，第一存储器控制器控制第一存储器以便不进行自刷新。 当从温度传感器接收到的第二温度信息指示检测到的温度处于预定温度范围时，第一存储器控制器向第一存储器输出自刷新命令。

公开(公告)号：US20100172193A1

公开(公告)日：2010-07-08

申请号：US12654739

申请日：2009-12-30

申请人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C7/1045 ,  G11C7/14 ,  G11C7/22 ,  G11C8/12

摘要： A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

摘要翻译： 一种半导体存储器件，包括：包括多个位线和多个虚拟位线的存储器阵列;偏置施加单元，被配置为向所述多个虚拟位线提供具有多个电压电平的偏置电压;待机电流测量单元 被配置为测量所述多个位线中的至少一个与所述多个虚拟位线中的至少一个之间的待机电流中的至少一个的值。 每个待机电流由偏置施加单元施加的每个偏置电压产生。

公开(公告)号：US08411520B2

公开(公告)日：2013-04-02

申请号：US12654739

申请日：2009-12-30

申请人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

发明人： Myung-Jae Lee ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C5/14 ,  G11C7/1045 ,  G11C7/14 ,  G11C7/22 ,  G11C8/12

摘要： A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.

摘要翻译： 一种半导体存储器件，包括：包括多个位线和多个虚拟位线的存储器阵列;偏置施加单元，被配置为向所述多个虚拟位线提供具有多个电压电平的偏置电压;待机电流测量单元 被配置为测量所述多个位线中的至少一个与所述多个虚拟位线中的至少一个之间的待机电流中的至少一个的值。 每个待机电流由偏置施加单元施加的每个偏置电压产生。

公开(公告)号：US20120063251A1

公开(公告)日：2012-03-15

申请号：US13228102

申请日：2011-09-08

申请人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

发明人： Jong Hyoung LIM ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC分类号： G11C7/06

CPC分类号： G11C7/12

摘要： A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

摘要翻译： 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US08144539B2

公开(公告)日：2012-03-27

申请号：US12645962

申请日：2009-12-23

申请人： Jong Hyoung Lim ,  Sang Seok Kang

发明人： Jong Hyoung Lim ,  Sang Seok Kang

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.

摘要翻译： 一种半导体存储器件包括：存储器核心单元，包括具有多个存储单元的存储单元阵列和用于感测和放大多个存储单元的数据的读出放大器;以及自刷新控制单元，用于施加至少一个第一核心电压 并且在第一自刷新模式下，在第一自刷新周期中控制自刷新操作，并且将至少一个第二核心电压施加到存储器核心单元并且控制自刷新操作 在第二自刷新模式下在每第二自刷新循环中执行。 在半导体存储器中，所述至少一个第一核心电压的电平高于所述至少一个第二核心电压中相应的第一核心电压的电平，并且所述第一自刷新周期比所述第二自刷新周期短。

公开(公告)号：US08619484B2

公开(公告)日：2013-12-31

申请号：US13228102

申请日：2011-09-08

申请人： Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

发明人： Jong Hyoung Lim ,  Sang Seok Kang ,  Hyung Shin Kwon

IPC分类号： G11C7/02

CPC分类号： G11C7/12

摘要： A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

摘要翻译： 半导体器件包括位线，互补位线，被配置为感测和放大位线和互补位线之间的电压差的读出放大器，以及电容调整电路，配置为调整互补位线的负载电容 响应于多个控制信号。

公开(公告)号：US20100165773A1

公开(公告)日：2010-07-01

申请号：US12645962

申请日：2009-12-23

申请人： Jong-Hyoung LIM ,  Sang Seok Kang

发明人： Jong-Hyoung LIM ,  Sang Seok Kang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.

摘要翻译： 一种半导体存储器件包括：存储器核心单元，包括具有多个存储单元的存储单元阵列和用于感测和放大多个存储单元的数据的读出放大器;以及自刷新控制单元，用于施加至少一个第一核心电压 并且在第一自刷新模式下，在第一自刷新周期中控制自刷新操作，并且将至少一个第二核心电压施加到存储器核心单元并且控制自刷新操作 在第二自刷新模式下在每第二自刷新循环中执行。 在半导体存储器中，所述至少一个第一核心电压的电平高于所述至少一个第二核心电压中相应的第一核心电压的电平，并且所述第一自刷新周期比所述第二自刷新周期短。