公开(公告)号：US20170040337A1

公开(公告)日：2017-02-09

申请号：US14987835

申请日：2016-01-05

申请人： Jong Won KIM ,  Seung Hyun LIM ,  Chang Seok KANG ,  Young Woo PARK ,  Dae Hoon BAE ,  Dong Seog EUN ,  Woo Sung LEE ,  Jae Duk LEE ,  Jae Woo LIM ,  HanMei CHOI

发明人： Jong Won KIM ,  Seung Hyun LIM ,  Chang Seok KANG ,  Young Woo PARK ,  Dae Hoon BAE ,  Dong Seog EUN ,  Woo Sung LEE ,  Jae Duk LEE ,  Jae Woo LIM ,  HanMei CHOI

IPC分类号： H01L27/115

CPC分类号： H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

摘要翻译： 存储器件包括多个通道区域，每个沟道区域在垂直于衬底的上表面的方向上延伸，多个栅极电极层和堆叠在衬底上的与沟道区相邻的多个绝缘层，每个栅电极 延伸不同长度，以及与多个栅电极层的第一端相邻的多个虚设通道区域，其中所述衬底包括形成在所述多个虚拟通道区域下方的衬底绝缘层。