公开(公告)号：US07499359B2

公开(公告)日：2009-03-03

申请号：US11354125

申请日：2006-02-15

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

IPC分类号： G11C7/00

CPC分类号： G01K7/01

摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

摘要翻译： 可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。 温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号， 列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和 长tRAS模式。 半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

公开(公告)号：US20060195289A1

公开(公告)日：2006-08-31

申请号：US11354125

申请日：2006-02-15

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

IPC分类号： G01K1/00

CPC分类号： G01K7/01

摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

公开(公告)号：US20070024351A1

公开(公告)日：2007-02-01

申请号：US11321875

申请日：2005-12-30

申请人： Yong-Gu Kang

发明人： Yong-Gu Kang

IPC分类号： G05F1/10

CPC分类号： G05F1/465

摘要： There is provided a circuit for generating an internal power voltage capable of stably controlling an internal power voltage before generating a reference voltage during an initial power-up operation of a semiconductor device. The circuit for generating an internal power voltage includes: an internal power reset controller for outputting a control signal in response to an activated reference signal and an external power voltage wherein the reference signal is activated after the external power voltage is inputted; and an internal power generator for generating the internal power voltage using the external power voltage in response to the activated reference signal wherein the internal power generator is disabled in response to the control signal.

摘要翻译： 提供了一种用于在半导体器件的初始上电操作期间产生能够稳定地控制内部电源电压的电路，该电路产生参考电压。 用于产生内部电源电压的电路包括：内部电源复位控制器，用于响应于激活的参考信号和外部电源电压输出控制信号，其中参考信号在输入外部电源电压之后被激活; 以及内部发电机，用于响应于激活的参考信号，利用外部电源电压产生内部电力电压，其中内部功率发生器响应于控制信号被禁用。

公开(公告)号：US08406074B2

公开(公告)日：2013-03-26

申请号：US12914164

申请日：2010-10-28

申请人： Yong-Gu Kang

发明人： Yong-Gu Kang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618

摘要： A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command.

摘要翻译： 半导体器件分别包括至少两个存储体的多个存储体组和与该多个存储体组一一对应的多个地址计数器。 响应于组组刷新命令执行所选择的组组的刷新操作。

公开(公告)号：US20110204953A1

公开(公告)日：2011-08-25

申请号：US12756772

申请日：2010-04-08

申请人： Yong-Gu Kang ,  Choung-Ki Song

发明人： Yong-Gu Kang ,  Choung-Ki Song

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.

摘要翻译： 电平移位器电路包括上拉单元，其配置为响应于以第一电压电平的幅度摆动的输入信号，将输出节点上拉至高于第一电压电平的第二电压电平;下拉单元 被配置为响应于输入信号来下拉输出节点，以及保护单元，连接在输出节点和下拉单元之间，以防止输出节点的电压被施加到下拉单元。

公开(公告)号：US07372311B2

公开(公告)日：2008-05-13

申请号：US11319720

申请日：2005-12-29

申请人： Yong-Gu Kang

发明人： Yong-Gu Kang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

摘要翻译： 提供了能够通过熔丝选项或EMRS输入来控制时钟占空比的DLL。 DLL包括第一时钟缓冲器，第二时钟缓冲器，第一延迟线，第二延迟线，移位寄存器，第一占空比控制单元，第二占空比控制单元，第一DLL驱动器，第二DLL驱动器， 延迟模型，相位比较器和移位控制单元。 在DLL中，第一占空比控制单元和第二占空比控制单元分别通过EMRS输入或熔丝选项来控制第一和第二延迟线的输出时钟的每个占空比。 因此，可以通过EMRS输入或保险丝选项来控制DLL时钟的占空比。

公开(公告)号：US08030987B2

公开(公告)日：2011-10-04

申请号：US12756772

申请日：2010-04-08

申请人： Yong-Gu Kang ,  Choung-Ki Song

发明人： Yong-Gu Kang ,  Choung-Ki Song

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.

摘要翻译： 电平移位器电路包括上拉单元，其配置为响应于以第一电压电平的幅度摆动的输入信号，将输出节点上拉至高于第一电压电平的第二电压电平;下拉单元 被配置为响应于输入信号来下拉输出节点，以及保护单元，连接在输出节点和下拉单元之间，以防止输出节点的电压被施加到下拉单元。

公开(公告)号：US07893738B2

公开(公告)日：2011-02-22

申请号：US12170243

申请日：2008-07-09

申请人： Yong-Gu Kang ,  Yong-Mi Kim

发明人： Yong-Gu Kang ,  Yong-Mi Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03K5/135 ,  H03L7/0814

摘要： A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

摘要翻译： 一种DLL电路，包括：第一时钟信号分配块，被配置为根据锁定完成信号是否被使能来选择性地分频参考时钟信号的频率;相位比较块，被配置为通过比较发送的时钟信号的相位来产生相位比较信号 从具有反馈时钟信号的第一时钟信号分割块和被配置为响应于相位比较信号产生锁定完成信号的操作模式设置块被描述。

公开(公告)号：US20060197565A1

公开(公告)日：2006-09-07

申请号：US11319720

申请日：2005-12-29

申请人： Yong-Gu Kang

发明人： Yong-Gu Kang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

摘要翻译： 提供了能够通过熔丝选项或EMRS输入来控制时钟占空比的DLL。 DLL包括第一时钟缓冲器，第二时钟缓冲器，第一延迟线，第二延迟线，移位寄存器，第一占空比控制单元，第二占空比控制单元，第一DLL驱动器，第二DLL驱动器， 延迟模型，相位比较器和移位控制单元。 在DLL中，第一占空比控制单元和第二占空比控制单元分别通过EMRS输入或熔丝选项来控制第一和第二延迟线的输出时钟的每个占空比。 因此，可以通过EMRS输入或保险丝选项来控制DLL时钟的占空比。