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    Temperature sensor instruction signal generator and semiconductor memory device having the same
    1.
    发明授权
    Temperature sensor instruction signal generator and semiconductor memory device having the same 失效
    温度传感器指令信号发生器和具有相同功能的半导体存储器件

    公开(公告)号：US07499359B2

    公开(公告)日：2009-03-03

    申请号：US11354125

    申请日：2006-02-15

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    IPC分类号： G11C7/00

    CPC分类号： G01K7/01

    摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

    摘要翻译： 可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。 温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号， 列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和 长tRAS模式。 半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

    INTERNAL REFERENCE VOLTAGE GENERATING CIRCUIT FOR REDUCING STANDBY CURRENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    INTERNAL REFERENCE VOLTAGE GENERATING CIRCUIT FOR REDUCING STANDBY CURRENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    内部基准电压产生电路，用于减少包括其中的待机电流和半导体存储器件

    公开(公告)号：US20070153590A1

    公开(公告)日：2007-07-05

    申请号：US11567826

    申请日：2006-12-07

    申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes, a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuits and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated white the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

    摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：通过电源电压输出所述参考电压的分压电路; 连接到分压电路的一端的下拉驱动器; 以及校准控制电路，其比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果控制下拉驱动器的导通电阻值。 内部参考电压产生电路白色运行，存储器控制器将信号输入到模式寄存器组（MRS）中以使能内部参考电压产生电路，并且MRS的输出信号被激活。

    Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same
    6.
    发明授权
    Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same 有权
    用于降低待机电流的内部参考电压发生电路和包括其的半导体存储器件

    公开(公告)号：US07515487B2

    公开(公告)日：2009-04-07

    申请号：US11567826

    申请日：2006-12-07

    申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

    摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：分压电路，通过电源电压输出基准电压; 连接到分压电路的一端的下拉驱动器; 以及校正控制电路，比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果来控制下拉驱动器的导通电阻值。 内部参考电压产生电路在存储器控制器将信号输入到模式寄存器组（MRS）中的情况下操作，以使能内部基准电压产生电路并且MRS的输出信号被激活。

    Semiconductor memory device for performing refresh operation
    7.
    发明申请
    Semiconductor memory device for performing refresh operation 有权
    用于执行刷新操作的半导体存储器件

    公开(公告)号：US20050105362A1

    公开(公告)日：2005-05-19

    申请号：US10954530

    申请日：2004-09-29

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622

    摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

    摘要翻译： 根据本发明的存储器件包括多个刷新模式和刷新控制器。 第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。 此外，第一刷新模式可以针对所选择的存储块执行刷新操作。 第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。 控制器可以在刷新操作中选择第一和第二刷新模式之一。

    Semiconductor memory device for performing refresh operation
    10.
    发明授权
    Semiconductor memory device for performing refresh operation 有权
    用于执行刷新操作的半导体存储器件

    公开(公告)号：US07180808B2

    公开(公告)日：2007-02-20

    申请号：US10954530

    申请日：2004-09-29

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622

    摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

    摘要翻译： 根据本发明的存储器件包括多个刷新模式和刷新控制器。 第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。 此外，第一刷新模式可以针对所选择的存储块执行刷新操作。 第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。 控制器可以在刷新操作中选择第一和第二刷新模式之一。