公开(公告)号：US07563656B2

公开(公告)日：2009-07-21

申请号：US11616542

申请日：2006-12-27

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136231 ,  H01L27/1288

摘要： A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

摘要翻译： 显示基板包括绝缘基板，薄膜晶体管，接触电极和像素电极。 薄膜晶体管包括控制电极，半导体图案，第一电极和第二电极。 控制电极在绝缘基板上。 半导体图案在控制电极上。 第一电极位于半导体图案上。 第二电极与半导体图案上的第一电极间隔开。 接触电极包括接触部分和底切部分。 接触部分电连接到第二电极以部分地暴露半导体图案。 底切部分电连接到接触部分以覆盖半导体图案。 像素电极通过接触电极的接触部分电连接到第二电极。

公开(公告)号：US07465613B2

公开(公告)日：2008-12-16

申请号：US11616542

申请日：2006-12-27

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

IPC分类号： H01L21/00 ,  H01L21/84

摘要： A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

公开(公告)号：US20100182525A1

公开(公告)日：2010-07-22

申请号：US12487928

申请日：2009-06-19

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

IPC分类号： G02F1/136 ,  H01L29/786

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136231 ,  H01L27/1288

摘要： A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

摘要翻译： 显示基板包括绝缘基板，薄膜晶体管，接触电极和像素电极。 薄膜晶体管包括控制电极，半导体图案，第一电极和第二电极。 控制电极在绝缘基板上。 半导体图案在控制电极上。 第一电极位于半导体图案上。 第二电极与半导体图案上的第一电极间隔开。 接触电极包括接触部分和底切部分。 接触部分电连接到第二电极以部分地暴露半导体图案。 底切部分电连接到接触部分以覆盖半导体图案。 像素电极通过接触电极的接触部分电连接到第二电极。

公开(公告)号：US08093594B2

公开(公告)日：2012-01-10

申请号：US12487928

申请日：2009-06-19

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

IPC分类号： H01L27/14

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136231 ,  H01L27/1288

摘要： A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

摘要翻译： 显示基板包括绝缘基板，薄膜晶体管，接触电极和像素电极。 薄膜晶体管包括控制电极，半导体图案，第一电极和第二电极。 控制电极在绝缘基板上。 半导体图案在控制电极上。 第一电极位于半导体图案上。 第二电极与半导体图案上的第一电极间隔开。 接触电极包括接触部分和底切部分。 接触部分电连接到第二电极以部分地暴露半导体图案。 底切部分电连接到接触部分以覆盖半导体图案。 像素电极通过接触电极的接触部分电连接到第二电极。

公开(公告)号：US07816712B2

公开(公告)日：2010-10-19

申请号：US11986330

申请日：2007-11-20

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L31/113

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/4908

摘要： A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

摘要翻译： 薄膜晶体管阵列及其制造方法包括由基板上的透明导电层形成的像素电极，由透明导电层形成的栅极线和基板上的不透明导电层，连接到栅极的栅电极 并且在基板上形成透明导电层和不透明导电层，覆盖栅极线和栅极的栅极绝缘层，形成在栅极绝缘层上以与栅电极重叠的半导体层，数据线， 与栅极线相交，连接到数据线的源电极与半导体层的一部分重叠，以及连接到像素电极以与半导体层的一部分重叠的漏电极。

公开(公告)号：US08173494B2

公开(公告)日：2012-05-08

申请号：US12890324

申请日：2010-09-24

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/4908

摘要： A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

摘要翻译： 薄膜晶体管阵列及其制造方法包括由基板上的透明导电层形成的像素电极，由透明导电层形成的栅极线和基板上的不透明导电层，连接到栅极的栅电极 并且在基板上形成透明导电层和不透明导电层，覆盖栅极线和栅极的栅极绝缘层，形成在栅极绝缘层上以与栅电极重叠的半导体层，数据线， 与栅极线相交，连接到数据线的源电极与半导体层的一部分重叠，以及连接到像素电极以与半导体层的一部分重叠的漏电极。

公开(公告)号：US20080116474A1

公开(公告)日：2008-05-22

申请号：US11986330

申请日：2007-11-20

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L33/00 ,  H01L21/02

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/4908

摘要： A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

摘要翻译： 薄膜晶体管阵列及其制造方法包括由基板上的透明导电层形成的像素电极，由透明导电层形成的栅极线和基板上的不透明导电层，连接到栅极的栅电极 并且在基板上形成透明导电层和不透明导电层，覆盖栅极线和栅极的栅极绝缘层，形成在栅极绝缘层上以与栅电极重叠的半导体层，数据线， 与栅极线相交，连接到数据线的源电极与半导体层的一部分重叠，以及连接到像素电极以与半导体层的一部分重叠的漏电极。

公开(公告)号：US07776633B2

公开(公告)日：2010-08-17

申请号：US11696097

申请日：2007-04-03

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel, including: forming gate lines on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines and drain electrodes on the semiconductor layers; depositing a passivation layer on the data lines and the drain electrodes; forming a first photoresist layer including a first portion and a second portion that is thinner than the first portion on the passivation layer; forming a first preliminary contact hole exposing the data lines by etching the passivation layer by using the first photoresist layer as a mask; removing the second portion of the first photoresist; forming a first contact hole by expanding the first preliminary contact hole and opening portions by etching the passivation layer by using the first portion of the first photoresist layer as a mask; depositing a conductor layer; and forming pixel electrodes in the opening portions and a first contact assistant member in the first contact hole by removing the first photoresist layer and the conductor layer located thereon.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括：在衬底上形成栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 形成第一光致抗蚀剂层，其包括比钝化层上的第一部分更薄的第一部分和第二部分; 通过使用第一光致抗蚀剂层作为掩模，形成通过蚀刻钝化层而暴露数据线的第一预接触孔; 去除第一光致抗蚀剂的第二部分; 通过使用第一光致抗蚀剂层的第一部分作为掩模，通过蚀刻钝化层来扩展第一预接触孔和开口部来形成第一接触孔; 沉积导体层; 以及通过去除位于其上的第一光致抗蚀剂层和导体层，在开口部分中形成像素电极和第一接触孔中的第一接触辅助部件。

公开(公告)号：US20080067603A1

公开(公告)日：2008-03-20

申请号：US11696097

申请日：2007-04-03

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Yoon ,  Jeong-Min Park ,  Doo-Hee Jung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel, including: forming gate lines on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines and drain electrodes on the semiconductor layers; depositing a passivation layer on the data lines and the drain electrodes; forming a first photoresist layer including a first portion and a second portion that is thinner than the first portion on the passivation layer; forming a first preliminary contact hole exposing the data lines by etching the passivation layer by using the first photoresist layer as a mask; removing the second portion of the first photoresist; forming a first contact hole by expanding the first preliminary contact hole and opening portions by etching the passivation layer by using the first portion of the first photoresist layer as a mask; depositing a conductor layer; and forming pixel electrodes in the opening portions and a first contact assistant member in the first contact hole by removing the first photoresist layer and the conductor layer located thereon.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括：在衬底上形成栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 形成第一光致抗蚀剂层，其包括比钝化层上的第一部分更薄的第一部分和第二部分; 通过使用第一光致抗蚀剂层作为掩模，形成通过蚀刻钝化层而暴露数据线的第一预接触孔; 去除第一光致抗蚀剂的第二部分; 通过使用第一光致抗蚀剂层的第一部分作为掩模，通过蚀刻钝化层来扩展第一预接触孔和开口部来形成第一接触孔; 沉积导体层; 以及通过去除位于其上的第一光致抗蚀剂层和导体层，在开口部分中形成像素电极和第一接触孔中的第一接触辅助部件。

公开(公告)号：US20070093005A1

公开(公告)日：2007-04-26

申请号：US11544738

申请日：2006-10-05

申请人： Joo-Han Kim ,  Soon-Kwon Lim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Eun-Guk Lee ,  Yang-Ho Bae ,  Byeong-Jin Lee ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Sung-Wook Kang

发明人： Joo-Han Kim ,  Soon-Kwon Lim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Eun-Guk Lee ,  Yang-Ho Bae ,  Byeong-Jin Lee ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Sung-Wook Kang

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/124 ,  H01L21/32139 ,  H01L27/1288

摘要： A thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the pixel electrode, a gate insulating film formed on the gate line, a semiconductor formed on the gate insulating film, a data line and a drain electrode formed on the gate insulating film, and a passivation layer formed on portions of the data line and the drain electrode. The gate line includes a first film formed on the same layer and with the same material as the pixel electrode and a second film formed on the first film.

摘要翻译： 薄膜晶体管阵列面板包括形成在基板上的像素电极，形成在像素电极上的栅极线，形成在栅极线上的栅极绝缘膜，形成在栅极绝缘膜上的半导体，数据线和漏极 形成在栅极绝缘膜上，以及形成在数据线和漏电极的部分上的钝化层。 栅线包括形成在同一层上并具有与像素电极相同的材料的第一膜和形成在第一膜上的第二膜。