公开(公告)号：US20130186677A1

公开(公告)日：2013-07-25

申请号：US13788916

申请日：2013-03-07

Applicant: Jong-Jin LEE

Inventor： Jong-Jin LEE

IPC: H05K3/00 ,  H05K1/02

CPC classification number: H05K3/0058 ,  H05K1/0271 ,  H05K3/022 ,  H05K3/382 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09136 ,  Y10T29/49124

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 在本发明的实施例中，制造印刷电路板的方法可以包括：提供一对导电层，其中一对导电层之一的一个表面的粗糙度与另一个导电层的一个表面的粗糙度不同 的一对导电层; 并且将所述一对导电层堆叠在电介质层上，使得所述一对导电层中的一个导电层的一个表面面对所述电介质层的一个表面，并且所述一对导电层中另一个表面的一个表面面向所述电介质层的另一个表面 。

公开(公告)号：US20070210368A1

公开(公告)日：2007-09-13

申请号：US11683364

申请日：2007-03-07

Applicant: Eun-Suk CHO ,  Jong-Jin LEE ,  Dong-Gun PARK ,  Jeong-Dong CHOE

Inventor： Eun-Suk CHO ,  Jong-Jin LEE ,  Dong-Gun PARK ,  Jeong-Dong CHOE

IPC: H01L21/3205 ,  H01L29/76

CPC classification number: H01L29/7885 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/7851 ,  H01L29/792

Abstract: A gate structure in a semiconductor device includes a tunnel insulation layer disposed on a substrate, a first charge trapping layer disposed on the tunnel insulation layer, a second charge trapping layer disposed on the first charge trapping layer, a dielectric layer disposed to cover the second charge trapping layer, and a conductive layer pattern disposed on the dielectric layer. The first charge trapping layer includes charge trapping sites for storing charges therein. The second charge trapping layer includes nanocrystals. The semiconductor device including the gate structure may have a sufficiently wide programming/erasing window and an improved data retention capability.

Abstract translation: 半导体器件中的栅极结构包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的第一电荷俘获层，设置在第一电荷俘获层上的第二电荷俘获层，设置成覆盖第二电荷俘获层的电介质层 电荷捕获层和设置在电介质层上的导电层图案。 第一电荷俘获层包括用于在其中存储电荷的电荷俘获位置。 第二电荷俘获层包括纳米晶体。 包括栅极结构的半导体器件可以具有足够宽的编程/擦除窗口和改进的数据保持能力。

公开(公告)号：US20100059267A1

公开(公告)日：2010-03-11

申请号：US12358543

申请日：2009-01-23

Applicant: Jong-Jin LEE

Inventor： Jong-Jin LEE

IPC: H05K1/05 ,  H05K3/00 ,  H01L23/14

CPC classification number: H05K3/0058 ,  H05K1/0271 ,  H05K3/022 ,  H05K3/382 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09136 ,  Y10T29/49124

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 在本发明的实施例中，制造印刷电路板的方法可以包括：提供一对导电层，其中一对导电层之一的一个表面的粗糙度与另一个导电层的一个表面的粗糙度不同 的一对导电层; 并且将所述一对导电层堆叠在电介质层上，使得所述一对导电层中的一个导电层的一个表面面对所述电介质层的一个表面，并且所述一对导电层中另一个表面的一个表面面向所述电介质层的另一个表面 。