公开(公告)号：US20160316558A1

公开(公告)日：2016-10-27

申请号：US15084992

申请日：2016-03-30

Applicant: IBIDEN CO., LTD.

Inventor： Shunsuke SAKAI ,  Toshiki FURUTANI ,  Kosuke IKEDA ,  Takema ADACHI ,  Takayuki KATSUNO

IPC: H05K1/11 ,  H05K3/18 ,  H05K1/09 ,  H05K3/00 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/11 ,  H01L21/486 ,  H01L23/12 ,  H01L23/145 ,  H01L23/49861 ,  H05K3/205 ,  H05K3/382 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0307

Abstract: A printed wiring board includes a resin insulating layer, a wiring conductor layer embedded in the insulating layer such that the wiring layer has first surface exposed from the insulating layer, and a conductor post formed in the insulating layer and on second surface of the wiring layer on the opposite side with respect to the first surface of the wiring layer such that the conductor post has side surface covered by the insulating layer and end surface exposed from the insulating layer on the opposite side with respect to the wiring layer. The conductor post is formed such that the side surface of the conductor post is a roughened side surface having surface roughness of first roughness R1, the end surface of the conductor post is a roughened end surface having surface roughness of second roughness R2, and the first and second roughnesses R1, R2 satisfy R1>R2.

Abstract translation: 印刷布线板包括树脂绝缘层，布置在绝缘层中的布线导体层，使得布线层具有从绝缘层露出的第一表面，以及形成在绝缘层中的导体柱和布线层的第二表面 在相对于布线层的第一表面的相对侧，使得导体柱具有被绝缘层覆盖的侧表面和相对于布线层的相对侧上的绝缘层暴露的端面。 导体柱形成为使得导体柱的侧表面是具有第一粗糙度R1的表面粗糙度的粗糙化侧表面，导体柱的端面是具有第二粗糙度R2的表面粗糙度的粗糙化端面，并且第一 第二粗糙度R1，R2满足R1> R2。

公开(公告)号：US20160174364A1

公开(公告)日：2016-06-16

申请号：US14970479

申请日：2015-12-15

Applicant: Amphenol Corporation

Inventor： Arthur E. Harkness, JR. ,  Eva M. Kenny-McDermott ,  Paul W. Farineau ,  Raymond A. Lavallee ,  Michael Fancher

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/38 ,  H05K3/46 ,  H05K3/00 ,  H05K3/22 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K3/4632 ,  H05K1/0242 ,  H05K1/0326 ,  H05K1/034 ,  H05K1/0346 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/116 ,  H05K3/0073 ,  H05K3/202 ,  H05K3/22 ,  H05K3/38 ,  H05K3/382 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/389 ,  H05K3/4658 ,  H05K3/4685 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/1194

Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.

Abstract translation: 描述了用于印刷电路板的高速互连以及用于形成高速互连的方法。 高速互连可以包括具有减小的表面粗糙度的导电膜的区域和已经被处理以改善与相邻绝缘层的接合的一个或多个区域。 粗糙度降低的区域可用于在PCB内携带高数据速率信号。 用于粘合处理的区域可以包括粗糙表面，促进粘附的化学处理和/或沉积以提高表面的润湿性和/或对固化的绝缘体的粘附的材料。

公开(公告)号：US20160050769A1

公开(公告)日：2016-02-18

申请号：US14778677

申请日：2014-03-25

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki YOSHIDA

IPC: H05K3/42 ,  C25D7/12 ,  C25D5/34 ,  C25D5/48 ,  H05K1/02 ,  C23C18/16 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  C25D3/38 ,  C25D5/10

CPC classification number: H05K3/421 ,  C23C18/1653 ,  C23C18/405 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  C25D7/123 ,  H05K1/0298 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/1423

Abstract: To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.

Abstract translation: 为了提供一种制造多层布线基板的方法，其中设置在其上的绝缘层和金属箔一体层压在其上形成有布线的内层材料上，其中在金属箔中形成有用于通孔的孔， 绝缘层，在形成基底化学镀层之后，通孔的孔填充有电解填充的镀层，其特征在于，在形成基底化学镀层之后，首先，填充电解液 形成电镀层的程度为通孔的孔未完全填充，然后在电解填充镀层的表面被蚀刻后，通孔的孔完全由电解填充镀层填充。

公开(公告)号：US08987603B2

公开(公告)日：2015-03-24

申请号：US13348708

申请日：2012-01-12

Applicant: Seiji Shirai ,  Kenichi Shimada ,  Motoo Asai

Inventor： Seiji Shirai ,  Kenichi Shimada ,  Motoo Asai

IPC: H05K1/03 ,  H05K3/46 ,  H05K3/42 ,  H05K3/10 ,  H05K3/38

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/382 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/0278 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: A multilayer printed wiring board includes a multilayered structure having conductor circuit layers and interlaminar insulative layers, the interlaminar insulative layers including an outermost interlaminar insulative layer, the conductor circuit layers including an outermost conductor circuit layer formed over the outermost interlaminar insulative, a filled-viahole formed in the outermost interlaminar insulative layer and having one or more metal plating fillings and completely closing a hole formed through the outermost interlaminar insulative layer such that the metal plating of the filled-viahole extends out of the hole and forms a substantially flat surface, and solder bumps including a first solder bump formed on the substantially flat surface of the filled-viahole and a second solder bump formed on a surface portion in the outermost conductor circuit layer. The substantially flat surface of the filled-viahole is leveled substantially at the same height as the surface portion of the outermost conductor circuit layer.

Abstract translation: 多层印刷线路板包括具有导体电路层和层间绝缘层的多层结构，所述层间绝缘层包括最外层间绝缘层，所述导体电路层包括形成在最外层间绝缘体上的最外导体电路层，填充通孔 形成在最外层间绝缘层中并且具有一个或多个金属电镀填充物并且完全闭合通过最外层间绝缘层形成的孔，使得填充通孔的金属镀层延伸出孔并形成基本平坦的表面，并且 焊料凸点包括形成在填充通孔的基本上平坦的表面上的第一焊料凸块和形成在最外导体电路层的表面部分上的第二焊料凸点。 填充通孔的基本上平坦的表面基本上与最外面的导体电路层的表面部分的高度平齐。

公开(公告)号：US08569873B2

公开(公告)日：2013-10-29

申请号：US13272930

申请日：2011-10-13

Applicant: Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

Inventor： Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

IPC: H01L23/02

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/025 ,  H05K3/242 ,  H05K3/382 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T156/10 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract translation: 可以通过增加电镀短截线导体的表面粗糙度来减轻电路板中的短截线共振。 粗化电镀短截线由于在较高频率下的皮肤效应而增加其电阻，这降低了传输线的品质因数并因此增加了阻尼因子，以减少在粗糙化之前形成的电镀短截线中发生的任何共振。 表面粗糙度可以通过各种方式增加，包括化学工艺，通过选择性地施加激光束，或通过在选定位置施加耐蚀刻材料。

公开(公告)号：US20130186677A1

公开(公告)日：2013-07-25

申请号：US13788916

申请日：2013-03-07

Applicant: Jong-Jin LEE

Inventor： Jong-Jin LEE

IPC: H05K3/00 ,  H05K1/02

CPC classification number: H05K3/0058 ,  H05K1/0271 ,  H05K3/022 ,  H05K3/382 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09136 ,  Y10T29/49124

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 在本发明的实施例中，制造印刷电路板的方法可以包括：提供一对导电层，其中一对导电层之一的一个表面的粗糙度与另一个导电层的一个表面的粗糙度不同 的一对导电层; 并且将所述一对导电层堆叠在电介质层上，使得所述一对导电层中的一个导电层的一个表面面对所述电介质层的一个表面，并且所述一对导电层中另一个表面的一个表面面向所述电介质层的另一个表面 。

公开(公告)号：US08225502B2

公开(公告)日：2012-07-24

申请号：US12102303

申请日：2008-04-14

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H01K3/10

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/382 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/098 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.

Abstract translation: 半导体器件100具有半导体芯片110倒装芯片安装在布线板120上的结构。布线板120具有布置多个布线层和多​​个绝缘层的多层结构，并且 第一电极焊盘130形成在芯片安装侧。 第一电极焊盘130的锥形表面132具有沿向上朝向焊接连接侧或芯片安装侧减小的取向的梯度。 因此，施加到焊料连接侧或芯片安装侧的力的保持力增大，此外，锥形表面132粘附到第一层的绝缘层的锥形内壁，使得与 绝缘层增加。

公开(公告)号：US20120032330A1

公开(公告)日：2012-02-09

申请号：US13272930

申请日：2011-10-13

Applicant: Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

Inventor： Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/025 ,  H05K3/242 ,  H05K3/382 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T156/10 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract translation: 可以通过增加电镀短截线导体的表面粗糙度来减轻电路板中的短截线共振。 粗化电镀短截线由于在较高频率下的皮肤效应而增加其电阻，这降低了传输线的品质因数并因此增加了阻尼因子，以减少在粗糙化之前形成的电镀短截线中发生的任何共振。 表面粗糙度可以通过各种方式增加，包括化学工艺，通过选择性地施加激光束，或通过在选定位置施加耐蚀刻材料。

公开(公告)号：US08110500B2

公开(公告)日：2012-02-07

申请号：US12255146

申请日：2008-10-21

Applicant: Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

Inventor： Bhyrav M. Mutnury ,  Moises Cases ,  Tae Hong Kim ,  Nanju Na

IPC: H01L21/44 ,  H01R9/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/025 ,  H05K3/242 ,  H05K3/382 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T156/10 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract translation: 可以通过增加电镀短截线导体的表面粗糙度来减轻电路板中的短截线共振。 粗化电镀短截线由于在较高频率下的皮肤效应而增加其电阻，这降低了传输线的品质因数并因此增加了阻尼因子，以减少在粗糙化之前形成的电镀短截线中发生的任何共振。 表面粗糙度可以通过各种方式增加，包括化学工艺，通过选择性地施加激光束，或通过在选定位置施加耐蚀刻材料。

公开(公告)号：US08039755B2

公开(公告)日：2011-10-18

申请号：US12465901

申请日：2009-05-14

Applicant: Wolfgang Bauer ,  Johannes Stahr

Inventor： Wolfgang Bauer ,  Johannes Stahr

IPC: H05K1/03

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/244 ,  H05K3/28 ,  H05K3/382 ,  H05K3/383 ,  H05K3/384 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit board element and production thereof are disclosed, whereby a noble metal is applied to a structured conductor layer on a circuit board substrate, comprising said conductor layer. The conductor layer is roughened on the surface, preferably after the structuring thereof and the noble metal applied as a layer, essentially on all of the structured roughened conductor layer, whereupon the noble metal layer surface is given a corresponding roughness.

Abstract translation: 公开了一种电路板元件及其制造方法，由此将贵金属应用于包括所述导体层的电路板基板上的结构化导体层。 导体层在表面上粗糙化，优选在其构造之后，并且作为层施加的贵金属基本上在所有结构化的粗糙导体层上，由此赋予贵金属层表面相应的粗糙度。