利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

133 条记录 (耗时 0.022 秒)

    Register controlled delay locked loop and its control method
    1.
    发明授权
    Register controlled delay locked loop and its control method 有权
    寄存器控制延迟锁定环及其控制方法

    公开(公告)号：US07088159B2

    公开(公告)日：2006-08-08

    申请号：US11020597

    申请日：2004-12-21

    申请人： Jong-Tae Kwak ,  Hyun-Woo Lee

    发明人： Jong-Tae Kwak ,  Hyun-Woo Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03L7/0818

    摘要： A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal; a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result; a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value; and a mixer controller for generating the weight value based on the phase detection signal.

    摘要翻译： 一种寄存器控制延迟锁定环（DLL），包括：粗延迟线，用于通过延迟外部时钟信号产生延迟的输入时钟信号; 一个精细的延迟线单元，用于接收延迟的输入时钟信号，以便产生第一精细延迟时钟信号和第二精细延迟时钟信号; 相位检测器，用于比较外部时钟信号和反馈时钟信号的相位，以便基于比较结果产生相位检测信号; 相位混合器，用于通过基于权重值混合第一精细延迟时钟信号和第二精细延迟时钟信号的相位来产生混合时钟信号; 以及混频器控制器，用于基于相位检测信号产生权重值。

    Register controlled delay locked loop and its control method
    2.
    发明申请
    Register controlled delay locked loop and its control method 有权

    公开(公告)号：US20060001465A1

    公开(公告)日：2006-01-05

    申请号：US11020597

    申请日：2004-12-21

    申请人： Jong-Tae Kwak ,  Hyun-Woo Lee

    发明人： Jong-Tae Kwak ,  Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818

    摘要： A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal; a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result; a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value; and a mixer controller for generating the weight value based on the phase detection signal.

    Digital delay locked loop capable of correcting duty cycle and its method
    3.
    发明授权
    Digital delay locked loop capable of correcting duty cycle and its method 有权
    数字延迟锁定环能够校正占空比及其方法

    公开(公告)号：US07385428B2

    公开(公告)日：2008-06-10

    申请号：US11646054

    申请日：2006-12-27

    申请人： Hyun-Woo Lee ,  Jong-Tae Kwak

    发明人： Hyun-Woo Lee ,  Jong-Tae Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

    摘要翻译： 一种用于调整时钟信号的装置，包括：时钟复用单元，用于接收外部时钟信号，外部时钟条信号和反馈时钟信号，以便选择外部时钟信号和外部时钟条信号之一作为 基于将所述外部时钟信号的相位与所述反馈时钟信号的相位进行比较的结果，所述时钟复用单元的输出信号; 以及用于响应于时钟多路复用单元的输出信号产生占空比校正时钟信号和反馈时钟信号的延迟锁定环（DLL）。

    Digital delay locked loop capable of correcting duty cycle and its method
    4.
    发明申请
    Digital delay locked loop capable of correcting duty cycle and its method 有权
    数字延迟锁定环能够校正占空比及其方法

    公开(公告)号：US20070103212A1

    公开(公告)日：2007-05-10

    申请号：US11646054

    申请日：2006-12-27

    申请人： Hyun-Woo Lee ,  Jong-Tae Kwak

    发明人： Hyun-Woo Lee ,  Jong-Tae Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

    摘要翻译： 一种用于调整时钟信号的装置，包括：时钟复用单元，用于接收外部时钟信号，外部时钟条信号和反馈时钟信号，以便选择外部时钟信号和外部时钟条信号之一作为 基于将所述外部时钟信号的相位与所述反馈时钟信号的相位进行比较的结果，所述时钟复用单元的输出信号; 以及用于响应于时钟多路复用单元的输出信号产生占空比校正时钟信号和反馈时钟信号的延迟锁定环（DLL）。

    Digital delay locked loop capable of correcting duty cycle and its method
    5.
    发明申请
    Digital delay locked loop capable of correcting duty cycle and its method 有权
    数字延迟锁定环能够校正占空比及其方法

    公开(公告)号：US20060001463A1

    公开(公告)日：2006-01-05

    申请号：US11020491

    申请日：2004-12-21

    申请人： Hyun-Woo Lee ,  Jong-Tae Kwak

    发明人： Hyun-Woo Lee ,  Jong-Tae Kwak

    IPC分类号： H03B19/00

    CPC分类号： H03K5/1565

    摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

    摘要翻译： 一种用于调整时钟信号的装置，包括：时钟复用单元，用于接收外部时钟信号，外部时钟条信号和反馈时钟信号，以便选择外部时钟信号和外部时钟条信号之一作为 基于将所述外部时钟信号的相位与所述反馈时钟信号的相位进行比较的结果，所述时钟复用单元的输出信号; 以及用于响应于时钟多路复用单元的输出信号产生占空比校正时钟信号和反馈时钟信号的延迟锁定环（DLL）。

    Digital delay locked loop capable of correcting duty cycle and its method
    6.
    发明授权
    Digital delay locked loop capable of correcting duty cycle and its method 有权

    公开(公告)号：US07161397B2

    公开(公告)日：2007-01-09

    申请号：US11020491

    申请日：2004-12-21

    申请人： Hyun-Woo Lee ,  Jong-Tae Kwak

    发明人： Hyun-Woo Lee ,  Jong-Tae Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

    Apparatus and method for distributing cloud computing resources using mobile devices
    8.
    发明授权
    Apparatus and method for distributing cloud computing resources using mobile devices 有权
    使用移动设备分发云计算资源的装置和方法

    公开(公告)号：US08843614B2

    公开(公告)日：2014-09-23

    申请号：US12857935

    申请日：2010-08-17

    申请人： Changwoo Yoon ,  Won Ryu ,  Hyun-Woo Lee ,  Kwihoon Kim ,  Nam-Kyung Lee ,  Seng-Kyoun Jo ,  Ho-Yeon Lee ,  Eui-Nam Huh ,  Seung-Min Han

    发明人： Changwoo Yoon ,  Won Ryu ,  Hyun-Woo Lee ,  Kwihoon Kim ,  Nam-Kyung Lee ,  Seng-Kyoun Jo ,  Ho-Yeon Lee ,  Eui-Nam Huh ,  Seung-Min Han

    IPC分类号： G06F15/173

    CPC分类号： G06F9/5072

    摘要： An apparatus for distributing mobile resources in a cloud computing environment includes: a resource register configured to analyze, when a request for mobile resource registration is inputted by a user, the requested resource and confirm if the resource is registerable; a provisioning manager configured to create a MVO, when the mobile resource is a registerable resource, and register the mobile resource; a metadata repository configured to store metadata information regarding the registered mobile resource; and a resource manager configured to control the provisioning manager, when the resource register receives a request for the resource registration, so as to create a MVO, register the resource, and store metadata regarding the registered mobile resource information.

    摘要翻译： 一种用于在云计算环境中分发移动资源的装置包括：资源寄存器，被配置为当用户输入移动资源注册的请求时分析所请求的资源并确认资源是否可注册; 配置管理器，被配置为当所述移动资源是可注册资源时创建MVO，并注册所述移动资源; 元数据存储库，被配置为存储关于注册的移动资源的元数据信息; 以及资源管理器，被配置为当所述资源注册器接收到所述资源注册的请求时，控制所述供应管理器，以便创建MVO，注册所述资源，以及存储关于所注册的移动资源信息的元数据。

    Method for transmitting ranging information in wireless communication system and terminal thereof
    9.
    发明授权
    Method for transmitting ranging information in wireless communication system and terminal thereof 有权
    用于在无线通信系统及其终端中发送测距信息的方法

    公开(公告)号：US08750162B2

    公开(公告)日：2014-06-10

    申请号：US13142842

    申请日：2010-01-05

    申请人： Hyun-Woo Lee ,  Min-Seok Noh ,  Yeong-Hyeon Kwon ,  Jin-Sam Kwak ,  Dong-Cheol Kim ,  Sung-Ho Moon ,  Seung-Hee Han

    发明人： Hyun-Woo Lee ,  Min-Seok Noh ,  Yeong-Hyeon Kwon ,  Jin-Sam Kwak ,  Dong-Cheol Kim ,  Sung-Ho Moon ,  Seung-Hee Han

    IPC分类号： H04W74/08

    CPC分类号： H04L27/2602 ,  H04L5/0007 ,  H04L27/2607 ,  H04W74/0891

    摘要： Disclosed is a method for configuring a ranging channel in various frame structures and using the same in a communication system. A ranging channel is effectively configured according to a data structure, namely, frame structure, transmitted and received between a mobile station (MS) and a base station (BS) in a wireless communication system, and ranging information is transmitted therethrough to thereby improve performance of a communication channel and resource efficiency. In the wireless communication system, a ranging channel is configured by using a time interval, such as an idle time, an idle symbol, an RTG, a TTG, and the like, not actually used for transmission of data or a signal in a data structure, namely, in a frame structure, transmitted and received between an MS and a BS, to transmit ranging information, so the channel performance and resource efficiency can be improved.

    摘要翻译： 公开了一种用于在各种帧结构中配置测距信道并在通信系统中使用该测量信道的方法。 根据无线通信系统中的移动台（MS）与基站（BS）之间发送和接收的数据结构，即帧结构，有效地配置测距信道，并且通过测距信息发送测距信息，从而提高性能 的沟通渠道和资源效率。 在无线通信系统中，通过使用不实际用于数据发送或数据中的信号的时间间隔（例如空闲时间，空闲符号，RTG，TTG等）来配置测距信道 结构，即在MS和BS之间发送和接收的帧结构中，发送测距信息，从而可以提高信道性能和资源效率。

    Apparatus and method for controlling uplink interference in a wireless communication system
    10.
    发明授权
    Apparatus and method for controlling uplink interference in a wireless communication system 有权
    用于控制无线通信系统中的上行链路干扰的装置和方法

    公开(公告)号：US08509697B2

    公开(公告)日：2013-08-13

    申请号：US13043260

    申请日：2011-03-08

    申请人： Ki-Seob Hong ,  Byung-Chan Ahn ,  Hyun-Woo Lee ,  Seung-Joo Maeng

    发明人： Ki-Seob Hong ,  Byung-Chan Ahn ,  Hyun-Woo Lee ,  Seung-Joo Maeng

    IPC分类号： H04B1/00 ,  H04B15/00

    CPC分类号： H04B15/00

    摘要： An apparatus and a method for controlling uplink interference in a wireless communication system. The method for controlling the uplink interference includes determining at least one interference signal power threshold determined by at least one neighbor Base Station (BS). The method also includes determining a transmit power offset for at least one serviced Mobile Station (MS) using the at least one interference signal power threshold. The method further includes sending the transmit power offset for the at least one MS to the at least one MS.

    摘要翻译： 一种用于控制无线通信系统中的上行链路干扰的装置和方法。 用于控制上行链路干扰的方法包括确定由至少一个相邻基站（BS）确定的至少一个干扰信号功率阈值。 该方法还包括使用至少一个干扰信号功率阈值确定至少一个服务移动站（MS）的发射功率偏移。 该方法还包括将至少一个MS的发射功率偏移发送到至少一个MS。