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公开(公告)号：US20120020167A1
公开(公告)日：2012-01-26
申请号：US13170713
申请日：2011-06-28
Applicant: Jong-hoon Lee , Jun-yong Park
Inventor： Jong-hoon Lee , Jun-yong Park
CPC classification number: G11C16/0483 , G11C16/10 , G11C16/3418
Abstract: A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.
Abstract translation: 闪存器件包括包括多个存储器单元的存储单元阵列; 产生并输出位线电压控制信号的位线电压控制信号发生器; 以及通过多个位线连接到存储单元阵列的页面缓冲单元，并且响应于从位线电压控制信号发生器输出的位线电压控制信号来控制多个位线的电压电平，其中多个位线 位线包括与第一位线相邻的第一位线和第二位线，其中在位线预充电操作期间，第一位线处于程序禁止状态，第二位线处于编程中 状态，所述页缓冲器单元响应于所述位线电压控制信号而增加所述第一位线的电压电平，其中所述第一位线的电压电平的增加导致所述第二位线的电压电平增加，以及 其中所述位线电压控制信号的电压电平不受所述闪存器件的电源电压的变化的影响。
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公开(公告)号：US08477538B2
公开(公告)日：2013-07-02
申请号：US13170713
申请日：2011-06-28
Applicant: Jong-hoon Lee , Jun-yong Park
Inventor： Jong-hoon Lee , Jun-yong Park
IPC: G11C11/34
CPC classification number: G11C16/0483 , G11C16/10 , G11C16/3418
Abstract: A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.
Abstract translation: 闪存器件包括包括多个存储器单元的存储单元阵列; 产生并输出位线电压控制信号的位线电压控制信号发生器; 以及通过多个位线连接到存储单元阵列的页面缓冲单元，并且响应于从位线电压控制信号发生器输出的位线电压控制信号来控制多个位线的电压电平，其中多个位线 位线包括与第一位线相邻的第一位线和第二位线，其中在位线预充电操作期间，第一位线处于程序禁止状态，第二位线处于编程中 状态，所述页缓冲器单元响应于所述位线电压控制信号而增加所述第一位线的电压电平，其中所述第一位线的电压电平的增加导致所述第二位线的电压电平增加，以及 其中所述位线电压控制信号的电压电平不受所述闪存器件的电源电压的变化的影响。
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公开(公告)号：US08149621B2
公开(公告)日：2012-04-03
申请号：US12585725
申请日：2009-09-23
Applicant: Bo-geun Kim , Dae-yong Kim , Jun-yong Park
Inventor： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
IPC: G11C11/34
CPC classification number: G11C29/12 , G11C16/04 , G11C2029/1208
Abstract: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
Abstract translation: 提供一种闪存设备和测试闪存设备的方法。 闪存器件可以包括包括多个位线的存储单元阵列，被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。 多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一，并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据，将读出的测试数据与 估计数据，以确定对应的位线是否处于通过或故障状态，并输出测试结果信号。 如果第一页中的相应位线处于故障状态，则读取存储单元阵列的第二页的测试数据时，维持测试结果信号的电压。
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公开(公告)号：US20100103743A1
公开(公告)日：2010-04-29
申请号：US12585725
申请日：2009-09-23
Applicant: Bo-geun Kim , Dae-yong Kim , Jun-yong Park
Inventor： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
CPC classification number: G11C29/12 , G11C16/04 , G11C2029/1208
Abstract: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
Abstract translation: 提供一种闪存设备和测试闪存设备的方法。 闪存器件可以包括包括多个位线的存储单元阵列，被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。 多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一，并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据，将读出的测试数据与 估计数据，以确定对应的位线是否处于通过或故障状态，并输出测试结果信号。 如果第一页中的相应位线处于故障状态，则读取存储单元阵列的第二页的测试数据时，维持测试结果信号的电压。
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