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    Digitally controlled oscillator
    1.
    发明授权
    Digitally controlled oscillator 有权
    数字控制振荡器

    公开(公告)号：US08040196B2

    公开(公告)日：2011-10-18

    申请号：US12570144

    申请日：2009-09-30

    申请人： Jong-shin Shin

    发明人： Jong-shin Shin

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315

    摘要： A digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

    摘要翻译： 数字控制振荡器包括环形振荡器，连接到环形振荡器的第一端子并且具有根据数字代码变化的电阻的并联电阻器组和连接到环形振荡器的第二端子的串联电阻器组，并且具有 电阻根据数字代码而变化。 环形振荡器的频率随并联电阻组的电阻的变化和串联电阻组的电阻根据数字代码而线性变化。

    DIGITALLY CONTROLLED OSCILLATOR
    2.
    发明申请
    DIGITALLY CONTROLLED OSCILLATOR 有权
    数字控制振荡器

    公开(公告)号：US20100090771A1

    公开(公告)日：2010-04-15

    申请号：US12570144

    申请日：2009-09-30

    申请人： Jong-shin Shin

    发明人： Jong-shin Shin

    IPC分类号： H03K3/00

    CPC分类号： H03K3/0315

    摘要： A digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

    摘要翻译： 数字控制振荡器包括环形振荡器，连接到环形振荡器的第一端子并且具有根据数字代码变化的电阻的并联电阻器组和连接到环形振荡器的第二端子的串联电阻器组，并且具有 电阻根据数字代码而变化。 环形振荡器的频率随并联电阻组的电阻的变化和串联电阻组的电阻根据数字代码而线性变化。

    Counter capable of holding and outputting a count value and phase locked loop having the counter
    5.
    发明授权
    Counter capable of holding and outputting a count value and phase locked loop having the counter 有权
    计数器能够保存并输出具有计数器的计数值和锁相环

    公开(公告)号：US07555094B2

    公开(公告)日：2009-06-30

    申请号：US11636452

    申请日：2006-12-11

    申请人： Jong-shin Shin ,  Ji-young Kim

    发明人： Jong-shin Shin ,  Ji-young Kim

    IPC分类号： G11C19/00

    CPC分类号： H03K23/58 ,  H03K21/38 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/18

    摘要： Example embodiments may provide a counter capable of outputting a count value after holding the count value for an amount of time and a phase locked loop (PLL) including the counter. The counter may include a selection unit that may selectively output a clock signal and a hold signal in response to a selection signal and a counting unit that may perform a counting operation in response to the clock signal and output a count value obtained by the counting operation after holding the count value for an amount of time in response to the hold signal. The counter may stably output an accurate count value regardless of transmission delays.

    摘要翻译： 示例性实施例可以提供一种能够在保持计数值一定量的时间之后输出计数值的计数器和包括计数器的锁相环（PLL）。 计数器可以包括选择单元，其可以响应于选择信号选择性地输出时钟信号和保持信号，以及可以响应于时钟信号执行计数操作的计数单元，并输出通过计数操作获得的计数值 在保持所述保持信号之后保持所述计数值一段时间。 无论传输延迟如何，计数器都可以稳定地输出精确的计数值。

    Semiconductor device, spread spectrum clock generator and method thereof
    6.
    发明授权
    Semiconductor device, spread spectrum clock generator and method thereof 有权
    半导体器件，扩频时钟发生器及其方法

    公开(公告)号：US07881419B2

    公开(公告)日：2011-02-01

    申请号：US11505360

    申请日：2006-08-17

    申请人： Jong-shin Shin

    发明人： Jong-shin Shin

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

    摘要： A semiconductor device, a spread spectrum clock generator and method thereof are provided. The example semiconductor device may include a frequency dividing unit receiving an output signal, generating a first feedback signal and a second feedback signal by dividing a frequency of the received output signal, and a phase offset unit outputting the output signal having a predetermined or desired phase difference with a reference signal in response to the second feedback signal, wherein the second feedback signal having a higher frequency than the first feedback signal. The example spread spectrum clock generator may include a plurality of frequency dividers which are connected in series and a selector selecting and outputting one of a plurality of output signals, each of the plurality of output signals having a different phase difference with respect to a reference signal, in response to at least one output from one or more of the plurality of frequency dividers. The example method may include receiving a reference signal with a first frequency, generating a feedback signal having a second frequency, the second frequency higher than the first frequency and outputting at least one of a sequentially selected set of output signals in response to the generated feedback signal.

    摘要翻译： 提供了半导体器件，扩频时钟发生器及其方法。 示例性半导体器件可以包括接收输出信号的分频单元，通过对接收的输出信号的频率进行分频来产生第一反馈信号和第二反馈信号;以及相位偏移单元，输出具有预定或期望相位的输出信号 与第二反馈信号的参考信号的差异，其中第二反馈信号具有比第一反馈信号更高的频率。 示例扩频时钟发生器可以包括串联连接的多个分频器和选择并输出多个输出信号之一的选择器，所述多个输出信号中的每一个相对于参考信号具有不同的相位差 响应于来自多个分频器中的一个或多个的至少一个输出。 示例性方法可以包括接收具有第一频率的参考信号，产生具有第二频率的反馈信号，第二频率高于第一频率，并且响应于所产生的反馈而输出顺序选择的一组输出信号中的至少一个 信号。

    Spread spectrum clock generator and method for generating a spread spectrum clock signal
    7.
    发明授权
    Spread spectrum clock generator and method for generating a spread spectrum clock signal 有权
    扩频时钟发生器和产生扩频时钟信号的方法

    公开(公告)号：US07558311B2

    公开(公告)日：2009-07-07

    申请号：US11205014

    申请日：2005-08-17

    申请人： Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

    发明人： Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

    IPC分类号： H04B1/00

    CPC分类号： H03L7/18 ,  H03B23/00 ,  H03L7/0891

    摘要： A spread spectrum clock generator (SSCG) and method of generating a spread spectrum clock (SSC) signal, in which the SSCG may include a controller outputting a given modulation voltage signal based on a difference between an average frequency of a first feedback signal and a comparison frequency signal input thereto, or based on comparison in total phase variations between a second feedback signal and the comparison frequency signal, and a sub-system for generating a first control voltage as a function of an input reference frequency signal and a second feedback signal input thereto. An adder may add the first control voltage signal and the modulation voltage signal to generate a second control voltage signal, and a voltage control oscillator (VCO) may generate the SSC signal based on the second control voltage signal.

    摘要翻译： 扩展频谱时钟发生器（SSCG）和产生扩频时钟（SSC）信号的方法，其中，SSCG可以包括控制器，该控制器基于第一反馈信号的平均频率和 或者基于第二反馈信号和比较频率信号之间的总相位变化的比较，以及用于产生作为输入参考频率信号和第二反馈信号的函数的第一控制电压的子系统 输入。 加法器可以添加第一控制电压信号和调制电压信号以产生第二控制电压信号，并且压控振荡器（VCO）可以基于第二控制电压信号产生SSC信号。

    Phase-locked loop integrated circuits having dual feedback control
    8.
    发明授权
    Phase-locked loop integrated circuits having dual feedback control 有权
    具有双重反馈控制的锁相环集成电路

    公开(公告)号：US08054115B2

    公开(公告)日：2011-11-08

    申请号：US12571868

    申请日：2009-10-01

    申请人： Jong-shin Shin

    发明人： Jong-shin Shin

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0895 ,  H03L7/087 ,  H03L7/18

    摘要： Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump.

    摘要翻译： 根据本发明的实施例的锁相环（PLL）集成电路提供双重反馈控制。 第一反馈控制利用将反馈时钟信号传递到相位频率检测器（PFD）的输入的常规锁相方案。 第二反馈控制使用自动频率校准器，其相对于在校准期间检测到的锁定频率来评估压控振荡器（VCO）的输出的频率，并向电荷泵提供单独的校准控制。

    Counter capable of holding and outputting a count value and phase locked loop having the counter
    9.
    发明申请
    Counter capable of holding and outputting a count value and phase locked loop having the counter 有权
    计数器能够保存并输出具有计数器的计数值和锁相环

    公开(公告)号：US20070133735A1

    公开(公告)日：2007-06-14

    申请号：US11636452

    申请日：2006-12-11

    申请人： Jong-shin Shin ,  Ji-young Kim

    发明人： Jong-shin Shin ,  Ji-young Kim

    IPC分类号： H03K23/00

    CPC分类号： H03K23/58 ,  H03K21/38 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/18

    摘要： Example embodiments may provide a counter capable of outputting a count value after holding the count value for an amount of time and a phase locked loop (PLL) including the counter. The counter may include a selection unit that may selectively output a clock signal and a hold signal in response to a selection signal and a counting unit that may perform a counting operation in response to the clock signal and output a count value obtained by the counting operation after holding the count value for an amount of time in response to the hold signal. The counter may stably output an accurate count value regardless of transmission delays.

    摘要翻译： 示例性实施例可以提供一种能够在保持计数值一定量的时间之后输出计数值的计数器和包括计数器的锁相环（PLL）。 计数器可以包括选择单元，其可以响应于选择信号选择性地输出时钟信号和保持信号，以及可以响应于时钟信号执行计数操作的计数单元，并输出通过计数操作获得的计数值 在保持所述保持信号之后保持所述计数值一段时间。 无论传输延迟如何，计数器都可以稳定地输出精确的计数值。

    Semiconductor device, spread spectrum clock generator and method thereof
    10.
    发明申请
    Semiconductor device, spread spectrum clock generator and method thereof 有权
    半导体器件，扩频时钟发生器及其方法

    公开(公告)号：US20070041486A1

    公开(公告)日：2007-02-22

    申请号：US11505360

    申请日：2006-08-17

    申请人： Jong-shin Shin

    发明人： Jong-shin Shin

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

    摘要： A semiconductor device, a spread spectrum clock generator and method thereof are provided. The example semiconductor device may include a frequency dividing unit receiving an output signal, generating a first feedback signal and a second feedback signal by dividing a frequency of the received output signal, and a phase offset unit outputting the output signal having a predetermined or desired phase difference with a reference signal in response to the second feedback signal, wherein the second feedback signal having a higher frequency than the first feedback signal. The example spread spectrum clock generator may include a plurality of frequency dividers which are connected in series and a selector selecting and outputting one of a plurality of output signals, each of the plurality of output signals having a different phase difference with respect to a reference signal, in response to at least one output from one or more of the plurality of frequency dividers. The example method may include receiving a reference signal with a first frequency, generating a feedback signal having a second frequency, the second frequency higher than the first frequency and outputting at least one of a sequentially selected set of output signals in response to the generated feedback signal.

    摘要翻译： 提供了半导体器件，扩频时钟发生器及其方法。 示例性半导体器件可以包括接收输出信号的分频单元，通过对接收的输出信号的频率进行分频来产生第一反馈信号和第二反馈信号;以及相位偏移单元，输出具有预定或期望相位的输出信号 与第二反馈信号的参考信号的差异，其中第二反馈信号具有比第一反馈信号更高的频率。 示例扩频时钟发生器可以包括串联连接的多个分频器和选择并输出多个输出信号之一的选择器，所述多个输出信号中的每一个相对于参考信号具有不同的相位差 响应于来自多个分频器中的一个或多个的至少一个输出。 示例性方法可以包括接收具有第一频率的参考信号，产生具有第二频率的反馈信号，第二频率高于第一频率，并且响应于所产生的反馈而输出顺序选择的一组输出信号中的至少一个 信号。