公开(公告)号：US20050114064A1

公开(公告)日：2005-05-26

申请号：US10911503

申请日：2004-08-05

申请人： Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

发明人： Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

IPC分类号： G11C29/00 ,  G01D3/00 ,  G11C29/34

CPC分类号： G11C29/34 ,  G11C2029/2602

摘要： A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.

摘要翻译： 一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据 第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。 一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。 另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

公开(公告)号：US5790465A

公开(公告)日：1998-08-04

申请号：US714577

申请日：1996-09-16

申请人： Jae-gu Roh ,  Soo-in Cho

发明人： Jae-gu Roh ,  Soo-in Cho

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/34

摘要： A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connected to input terminals of a second half of the plurality of word line drivers. The first and second tests circuits are sequentially activated to perform a burn-in test for all the memory cells.

摘要翻译： 一种具有第一测试电路的半导体存储器件的老化测试电路，其具有连接到多个字线驱动器的前半部分的输入端的输出端子。 第二测试电路具有连接到多个字线驱动器的后半部分的输入端子的输出端子。 第一和第二测试电路被顺序激活，以对所有存储器单元执行老化测试。

公开(公告)号：US06983010B1

公开(公告)日：2006-01-03

申请号：US09542042

申请日：2000-03-31

申请人： Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

发明人： Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

IPC分类号： H03H7/30

CPC分类号： G11C7/1057 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H01L27/088 ,  H04L27/01

摘要： A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed. Therefore, according to the semiconductor device including the high frequency equalizer, the lost high frequency component of data can be restored even at a high data transmission speed.

摘要翻译： 提供了使用解复用技术的高频均衡器和使用其的半导体器件。 高频均衡器将通过输入和输出端输入的输入数据解复用为多个输入数据项，每个具有与输入数据周期相同的时间差。 均衡器恢复多路复用输入数据项的丢失的高频数据分量，复用恢复的多个数据项，并逐个依次输出恢复的数据项。 因此，即使通过数据传输速度的增加来减少输入数据的周期，也可以使用这种高频均衡器来允许足够的时间来恢复丢失的高频分量。 使用该高频均衡器，即使在高数据传输速度下也可以正确地恢复丢失的高频分量。 因此，根据包括高频均衡器的半导体器件，即使在高数据传输速度下也可以恢复数据的丢失高频分量。

公开(公告)号：US5130580A

公开(公告)日：1992-07-14

申请号：US550997

申请日：1990-07-11

申请人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

发明人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.

摘要翻译： 一种读出放大器驱动电路，用于通过接通/断开连接在外部电压Vcc端子和接地电压Vss端子之间的驱动晶体管来控制高密度半导体存储器件的读出放大器，包括：偏置电路，包括MOS晶体管，连接到 驱动MOS晶体管与其形成电流镜像电路，其由读出放大器使能时钟控制，并且具有MOS晶体管的恒定电流源，其中Vcc和Vss之间的中间电平的偏置电压被施加到其栅极端子。 偏置电路连接到驱动晶体管的栅极端子，以控制驱动晶体管的栅极电压，从而降低读出放大器驱动信号的峰值电流。 此外，在具有线性双斜率的波形中产生驱动信号，导致功率噪声的降低。 偏置电路连接到具有比较器电路的钳位电路，以钳位读出放大器驱动电路的有效恢复电压，使得有效恢复电压可以保持在内部电压（大约4V）的水平，从而防止 通过使感测放大器仅用于主动恢复操作，从而消除了电池装置特性的失真，并消除了额外待机电流的必要性。 此外，读出放大器驱动电路包括一个恒定电路，该恒定电路包括被依次激活的两个或多个电流镜电路，从而使读出放大器驱动信号具有稳定的线性双斜率。