Semiconductor Device With An Image Sensor And Method For The Manufacture Of Such A Device
    2.
    发明申请
    Semiconductor Device With An Image Sensor And Method For The Manufacture Of Such A Device 有权
    具有图像传感器的半导体器件及其制造方法

    公开(公告)号:US20080197386A1

    公开(公告)日:2008-08-21

    申请号:US11912697

    申请日:2006-04-26

    IPC分类号: H01L27/146 H01L21/8238

    摘要: The invention relates to a semiconductor device with a semiconductor body (12) with an image sensor comprising a two-dimensional matrix of pixels (1) each comprising a radiation-sensitive element (2) with a charge accumulating semiconductor region (2A) and coupled to a number of MOS field effect transistors (3), in which in the semiconductor body (12) an isolation region (4) is sunken for the separation of neighboring pixels (1) underneath which a further semiconductor region (5) with an enlarged doping concentration is formed. According to the invention the further semiconductor region (5) is sunken in the surface of the semiconductor body (12) and wider than the isolation region (4). Preferably the isolation region (4) is merely located there where a radiation sensitive element (2) borders on the MOS transistors (3) of a neighboring pixel (1) and there where two neighboring pixels (1) border on each other with their radiation sensitive elements (2) another sunken semiconductor region (6) with an enlarged doping concentration is located. Such a device (10) has a low leakage current and a large radiation sensitivity and charge storage capacity.

    摘要翻译: 本发明涉及具有半导体本体(12)的半导体器件,该半导体器件(12)具有图像传感器,该图像传感器包括像素(2)的二维矩阵,每个像素阵列包括具有电荷累积半导体区域(2A)的辐射敏感元件(2) 耦合到多个MOS场效应晶体管(3),其中在半导体主体(12)中,隔离区域(4)凹陷以分离其下方的相邻像素(1),其中另外的半导体区域(5)具有 形成增大的掺杂浓度。 根据本发明,另外的半导体区域(5)在半导体本体(12)的表面凹陷并且比隔离区域(4)更宽。 优选地,隔离区域(4)仅位于辐射敏感元件(2)与相邻像素(1)的MOS晶体管(3)相邻并且其中两个相邻像素(1)以其辐射彼此相接的位置 敏感元件(2)定位了具有增大的掺杂浓度的另一凹陷半导体区域(6)。 这种装置(10)具有低泄漏电流和大的辐射灵敏度和电荷存储容量。

    ENHANCED HVPMOS
    5.
    发明申请
    ENHANCED HVPMOS 有权
    增强HVPMOS

    公开(公告)号:US20120032262A1

    公开(公告)日:2012-02-09

    申请号:US12851256

    申请日:2010-08-05

    IPC分类号: H01L29/78 H01L21/336

    摘要: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

    摘要翻译: 公开了具有受控n型掩埋层(NBL)的p沟道LDMOS器件。 定义浅沟槽隔离(STI)氧化,部分或全部覆盖漂移区域长度。 可以用p阱掩模定义的NBL层连接到n阱扩散,从而为通过冲击电离产生的电子提供排气路径。 对Kirk效应的高度免疫力也得以实现,从而大大改善了安全操作区(SOA)。 漂移区内部NBL的加入支持空间电荷耗尽区,增加了RESURF的有效性,从而改善了BV。 可以设置最佳NBL植入剂量,以确保在漂移区域(电荷平衡条件)中n和p掺杂之间的完全补偿电荷平衡。 可以进一步增加p阱注入剂量以维持电荷平衡,这导致Rdson降低。

    Enhanced HVPMOS
    6.
    发明授权
    Enhanced HVPMOS 有权
    增强HVPMOS

    公开(公告)号:US08729629B2

    公开(公告)日:2014-05-20

    申请号:US13539033

    申请日:2012-06-29

    IPC分类号: H01L29/78 H01L21/336

    摘要: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

    摘要翻译: 公开了具有受控n型掩埋层(NBL)的p沟道LDMOS器件。 定义浅沟槽隔离(STI)氧化,部分或全部覆盖漂移区域长度。 可以用p阱掩模定义的NBL层连接到n阱扩散,从而为通过冲击电离产生的电子提供排气路径。 对Kirk效应的高度免疫力也得以实现,从而大大改善了安全操作区(SOA)。 漂移区内部NBL的加入支持空间电荷耗尽区,增加了RESURF的有效性,从而改善了BV。 可以设置最佳NBL植入剂量,以确保在漂移区域(电荷平衡条件)中n和p掺杂之间的完全补偿电荷平衡。 可以进一步增加p阱注入剂量以维持电荷平衡,这导致Rdson降低。

    Enhanced HVPMOS
    8.
    发明授权
    Enhanced HVPMOS 有权
    增强HVPMOS

    公开(公告)号:US08217452B2

    公开(公告)日:2012-07-10

    申请号:US12851256

    申请日:2010-08-05

    IPC分类号: H01L29/78 H01L21/336

    摘要: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

    摘要翻译: 公开了具有受控n型掩埋层(NBL)的p沟道LDMOS器件。 定义浅沟槽隔离(STI)氧化,部分或全部覆盖漂移区域长度。 可以用p阱掩模定义的NBL层连接到n阱扩散,从而为通过冲击电离产生的电子提供排气路径。 对Kirk效应的高度免疫力也得以实现,从而大大改善了安全操作区(SOA)。 漂移区内部NBL的加入支持空间电荷耗尽区,增加了RESURF的有效性,从而改善了BV。 可以设置最佳NBL植入剂量,以确保在漂移区域(电荷平衡条件)中n和p掺杂之间的完全补偿电荷平衡。 可以进一步增加p阱注入剂量以维持电荷平衡,这导致Rdson降低。