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公开(公告)号：US07099963B2
公开(公告)日：2006-08-29
申请号：US10385042
申请日：2003-03-10
IPC分类号： G06F11/34
CPC分类号： G06F11/3034 , G06F11/3072 , G11B27/36
摘要： A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.
摘要翻译： 提供了一种用于监视嵌入式盘控制器中的多个组件的历史模块，其中操作上耦合到第一总线的第一主处理器和可操作地耦合到第二总线的第二处理器。 历史模块包括事件控制模块，其接收使历史模块停止记录组件信息的断点条件; 以及允许在嵌入式磁盘控制器中选择或取消某些组件的第一寄存器。 第一个寄存器还可以存储触发模式值，该值指定在检测到断点条件后在历史模块缓冲区中进行的条目数。
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公开(公告)号：US08788641B1
公开(公告)日：2014-07-22
申请号：US11936631
申请日：2007-11-07
IPC分类号： G06F15/173
CPC分类号： G06F13/126 , Y02D10/14
摘要： Systems, apparatuses, and methods for an interface module to interface with an enclosure services processor are described herein. The interface module may include one or more state machines configured to provide an enclosure service operation. Provision of this enclosure service operation may be at least partially unsupervised by a control processor requesting the enclosure service operation. Other embodiments may be described and claimed.
摘要翻译： 本文描述了用于接口模块与机箱服务处理器接口的系统，设备和方法。 接口模块可以包括被配置为提供机箱服务操作的一个或多个状态机。 可以由控制处理器至少部分地提供这种机箱服务操作，该控制处理器请求机箱服务操作。 可以描述和要求保护其他实施例。
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3.发明授权Method and system for using an external bus controller in embedded disk controllers 有权在嵌入式磁盘控制器中使用外部总线控制器的方法和系统公开(公告)号：US07219182B2
公开(公告)日：2007-05-15
申请号：US10385056
申请日：2003-03-10
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system and method for an embedded disk controller is provided. The embedded disk controller includes a main processor in communication with a first bus. A second processor communicates with a second bus. An external bus interface controller (“EBC”) located on the embedded disk controller manages a plurality of memory devices external to the system embedded disk controller via an external bus interface and coupled to the first bus and an external bus. Each of the plurality of memory devices has at least one of different timing characteristics and different data widths. The EBC is coupled to the first bus and stores at least one of a segment descriptor register and at least a device range register.
摘要翻译： 提供了一种用于嵌入式磁盘控制器的系统和方法。 嵌入式盘控制器包括与第一总线通信的主处理器。 第二处理器与第二总线进行通信。 位于嵌入式磁盘控制器上的外部总线接口控制器（“EBC”）通过外部总线接口管理系统嵌入式磁盘控制器外部的多个存储器件，并耦合到第一总线和外部总线。 多个存储器件中的每一个具有不同的定时特性和不同的数据宽度中的至少一个。 EBC耦合到第一总线并且存储段描述符寄存器和至少一个器件范围寄存器中的至少一个。
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4.发明授权Method and system for using an external bus controller in embedded disk controllers 有权在嵌入式磁盘控制器中使用外部总线控制器的方法和系统公开(公告)号：US07853747B2
公开(公告)日：2010-12-14
申请号：US11803458
申请日：2007-05-15
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.
摘要翻译： 嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。 外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件 通过外部总线。 多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。
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公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译： 提供了一种嵌入式磁盘控制器的系统。 该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。 第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。
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公开(公告)号：US5048024A
公开(公告)日：1991-09-10
申请号：US403638
申请日：1989-09-06
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A novel partitioned parity check and regeneration circuit is provided for receiving an input data word which is partitioned and the partitioned bits are stored in a partitioning register to provide a subset input data word of fewer data bits than the input data word. Parity register means including a parity register are associated with the partitioning register to provide a parity check of the partitioned data word and for generating an error detect signal when the data bits in the partitioning register are not properly latched. The parity bits stored in the associated parity register are employed with associated output logic to generate regenerated parity bits associated with the output of the data bits in the partitioning register to preserve the integrity of the data.
摘要翻译： 提供了一种新颖的分区奇偶校验和再生电路，用于接收分割的输入数据字，并将分割的比特存储在分区寄存器中，以提供比输入数据字少的数据比特的子集输入数据字。 包括奇偶校验寄存器的奇偶校验寄存器与分区寄存器相关联，以提供分区数据字的奇偶校验，并且当分区寄存器中的数据位未正确锁存时产生错误检测信号。 存储在相关联的奇偶校验寄存器中的奇偶校验位与相关联的输出逻辑一起使用以产生与分区寄存器中的数据位的输出相关联的再生奇偶校验位，以保持数据的完整性。
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7.发明授权公开(公告)号：US06457067B1
公开(公告)日：2002-09-24
申请号：US09216303
申请日：1998-12-18
IPC分类号： G06F300
CPC分类号： G11C29/024 , G11C29/02
摘要： An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.
摘要翻译： 提供了一种用于检测存储设备的寻址逻辑内的故障发生的改进的故障检测系统和方法。 存储到存储设备内的所选地址的数据包括所选地址的副本。 在随后的读取操作期间，从存储器读取地址的副本，并与用于执行存储器访问的读取地址进行比较。 如果地址不一致，则在存储设备的控制逻辑内发生潜在寻址故障。 故障检测系统特别适用于具有相对较少数量可寻址位置的存储设备，每个存储设备包含相对大量的位。 根据本发明的一个实施例，存储设备是用作队列的通用寄存器阵列（GRA）。
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公开(公告)号：US5828823A
公开(公告)日：1998-10-27
申请号：US845643
申请日：1997-04-25
申请人： Larry L. Byers , Gary R. Robeck
发明人： Larry L. Byers , Gary R. Robeck
CPC分类号： G06F11/1441
摘要： A method and apparatus for efficiently download and/or upload critical data elements between a computer's memory to/from a data save disk system, when a failure of a primary power source is detected. This is accomplished by coupling the data save disk system directly to the memory module such that the data elements in the memory module may be downloaded directly to the data save disk system without any intervention by a host computer. This configuration may have a number of advantages. First, the speed at which the data elements may be downloaded from the memory module to the data save disk system may be enhanced due to the direct coupling therebetween. Second, significant power savings may be realized because only the memory module and the data save disk system need to be powered by a secondary power source to effect the download operation. This may significantly increase the amount of time that the secondary power source may power the system thereby increasing the number of data elements that can be downloaded from the memory.
摘要翻译： 当检测到主电源的故障时，用于在数据存储盘系统的计算机存储器之间有效地下载和/或上传关键数据元素的方法和装置。 这是通过将数据保存磁盘系统直接耦合到存储器模块来实现的，使得存储器模块中的数据元素可以直接下载到数据保存磁盘系统，而无需主计算机的任何干预。 该配置可以具有许多优点。 首先，可以通过它们之间的直接耦合来增强数据元素可以从存储器模块下载到数据保存盘系统的速度。 第二，可以实现显着的功率节省，因为只有存储器模块和数据保存磁盘系统需要由次级电源供电才能实现下载操作。 这可以显着增加次级电源可以为系统供电的时间量，从而增加可以从存储器下载的数据元素的数量。
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9.发明授权Method and apparatus for dynamically testing a memory within a computer system 失效用于在计算机系统内动态测试存储器的方法和装置
公开(公告)号：US5784382A
公开(公告)日：1998-07-21
申请号：US396679
申请日：1995-03-01
CPC分类号： G11C29/20
摘要： A method and apparatus for increasing the efficiency of a dynamic read and/or write operation of a memory element within a computer system. The dynamic read and/or write operation may be performed when the computer system is in a functional mode or a test mode. The present invention may reduce the number of bits that are required to be serially shifted into a design by providing an auto-increment block. It is recognized that most multi-word access to a memory are made to sequential address locations within the memory. The auto-increment block takes advantage of this and automatically manipulates the address thereby not requiring subsequent addresses to be serially shifted into the design. Further, the control word may be stored within the design for subsequent accesses. That is, the support controller may shift a starting address and a control word into the design. The addresses for subsequent accesses may be generated by the auto-increment block, thereby only requiring that the support controller shift a data word to/from the design. This may significantly reduce the time necessary perform the subsequent read and/or write operations.
摘要翻译： 一种用于提高计算机系统内的存储元件的动态读取和/或写入操作的效率的方法和装置。 当计算机系统处于功能模式或测试模式时，可以执行动态读取和/或写入操作。 本发明可以通过提供自动增量块来减少串行转换到设计中所需的位数。 可以认识到，大多数对存储器的多字访问是对存储器内的顺序地址位置进行的。 自动增量块利用此功能，并自动操作地址，从而不需要将后续地址串行转换到设计中。 此外，控制字可以存储在设计中用于随后的访问。 也就是说，支持控制器可以将起始地址和控制字转移到设计中。 用于后续访问的地址可以由自动递增块生成，从而仅需要支持控制器将数据字移向/从设计。 这可能会显着减少执行后续读取和/或写入操作所需的时间。
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10.发明授权Method and apparatus for indicating the severity of a fault within a computer system 失效用于指示计算机系统内的故障严重性的方法和装置
公开(公告)号：US5596716A
公开(公告)日：1997-01-21
申请号：US396953
申请日：1995-03-01
CPC分类号： G06F11/0772 , G06F11/0721 , G06F11/22
摘要： A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.
摘要翻译： 一种用于有效地识别和指示计算机系统内的故障严重性的方法和装置。 在本发明的示例性实施例中，计算机系统的电路可以被划分成多个组。 每个组可能包含可能导致相同故障类型的电路。 例如，当在其中检测到故障时可能对计算机系统的正常操作具有最小影响的预定电路可以在第一组中提供。 类似地，当在其中检测到故障时可能对计算机系统的正常操作具有直接影响的预定电路可以在第二组中提供。 每个组可以向支持控制器提供错误优先级信号。 支持控制器可以解释由组数提供的错误优先级信号的数量，并且可以确定在其上采取校正动作的适当时间。
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