公开(公告)号：US5784712A

公开(公告)日：1998-07-21

申请号：US396677

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F9/312 ,  G06F9/345 ,  G06F13/16 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F13/1631 ,  G06F9/345 ,  G06F9/3861

摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

摘要翻译： 一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。 在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。 也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。 随后的地址可以由自动增量块自动生成。

公开(公告)号：US5680537A

公开(公告)日：1997-10-21

申请号：US396678

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

IPC分类号： G06F11/22 ,  G06F13/00

CPC分类号： G06F11/2268

摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

摘要翻译： 一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。 控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。 控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。 这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。

公开(公告)号：US5784382A

公开(公告)日：1998-07-21

申请号：US396679

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  Randy L. DeGarmo ,  Paul A. LaBerge

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  Randy L. DeGarmo ,  Paul A. LaBerge

IPC分类号： G11C29/20 ,  G01R31/28 ,  G06F12/00

CPC分类号： G11C29/20

摘要： A method and apparatus for increasing the efficiency of a dynamic read and/or write operation of a memory element within a computer system. The dynamic read and/or write operation may be performed when the computer system is in a functional mode or a test mode. The present invention may reduce the number of bits that are required to be serially shifted into a design by providing an auto-increment block. It is recognized that most multi-word access to a memory are made to sequential address locations within the memory. The auto-increment block takes advantage of this and automatically manipulates the address thereby not requiring subsequent addresses to be serially shifted into the design. Further, the control word may be stored within the design for subsequent accesses. That is, the support controller may shift a starting address and a control word into the design. The addresses for subsequent accesses may be generated by the auto-increment block, thereby only requiring that the support controller shift a data word to/from the design. This may significantly reduce the time necessary perform the subsequent read and/or write operations.

摘要翻译： 一种用于提高计算机系统内的存储元件的动态读取和/或写入操作的效率的方法和装置。 当计算机系统处于功能模式或测试模式时，可以执行动态读取和/或写入操作。 本发明可以通过提供自动增量块来减少串行转换到设计中所需的位数。 可以认识到，大多数对存储器的多字访问是对存储器内的顺序地址位置进行的。 自动增量块利用此功能，并自动操作地址，从而不需要将后续地址串行转换到设计中。 此外，控制字可以存储在设计中用于随后的访问。 也就是说，支持控制器可以将起始地址和控制字转移到设计中。 用于后续访问的地址可以由自动递增块生成，从而仅需要支持控制器将数据字移向/从设计。 这可能会显着减少执行后续读取和/或写入操作所需的时间。

公开(公告)号：US5596716A

公开(公告)日：1997-01-21

申请号：US396953

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F11/07 ,  G06F11/22 ,  G06F11/08 ,  G06F11/14

CPC分类号： G06F11/0772 ,  G06F11/0721 ,  G06F11/22

摘要： A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.

摘要翻译： 一种用于有效地识别和指示计算机系统内的故障严重性的方法和装置。 在本发明的示例性实施例中，计算机系统的电路可以被划分成多个组。 每个组可能包含可能导致相同故障类型的电路。 例如，当在其中检测到故障时可能对计算机系统的正常操作具有最小影响的预定电路可以在第一组中提供。 类似地，当在其中检测到故障时可能对计算机系统的正常操作具有直接影响的预定电路可以在第二组中提供。 每个组可以向支持控制器提供错误优先级信号。 支持控制器可以解释由组数提供的错误优先级信号的数量，并且可以确定在其上采取校正动作的适当时间。

公开(公告)号：US5511164A

公开(公告)日：1996-04-23

申请号：US396952

申请日：1995-03-01

申请人： Terry J. Brunmeier ,  Larry L. Byers ,  John A. Miller ,  Gary R. Robeck

发明人： Terry J. Brunmeier ,  Larry L. Byers ,  John A. Miller ,  Gary R. Robeck

IPC分类号： G06F11/07 ,  G06F11/00

CPC分类号： G06F11/073 ,  G06F11/0793

摘要： A method and apparatus for identify the source and nature of an error, without aborting the operation of the computer system. In one embodiment of the present invention, the source of the error may be a hardware element and the nature of the error may be identified as either fatal or non-fatal. If the nature of the error is considered non-fatal, the present invention may correct the error and continue the operation of the computer system. This may allow detected errors to be handled immediately after they occur, rather than aborting the operation of the computer system and waiting for a support controller or the like to analyze the error. This may significantly enhance the reliability and performance of a corresponding computer system. This may be especially important during time critical operations. Further, since the operation of the computer system may be aborted a fewer number of times, the present invention may minimize the amount of data loss. This may be particularly important for high reliability computer applications, including banking applications and airline reservation applications, where the integrity of the data base is of the utmost importance.

摘要翻译： 用于识别错误的来源和性质的方法和装置，而不中止计算机系统的操作。 在本发明的一个实施例中，错误的来源可以是硬件元件，并且错误的性质可以被识别为致命的或非致命的。 如果错误的性质被认为是非致命的，则本发明可以纠正错误并继续计算机系统的操作。 这可以允许检测到的错误在它们发生之后立即被处理，而不是中止计算机系统的操作并等待支持控制器等来分析错误。 这可以显着提高相应计算机系统的可靠性和性能。 这在时间关键操作中可能尤其重要。 此外，由于计算机系统的操作可以中止更少的次数，本发明可以最小化数据丢失的量。 这对于可靠性高的计算机应用尤其重要，包括银行应用和航空预订应用，数据库的完整性至关重要。