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1.发明申请Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US20060192266A1
公开(公告)日：2006-08-31
申请号：US11067983
申请日：2005-02-28
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。
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2.发明授权Semiconductor memory having charge trapping memory cells and fabrication method thereof 失效具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US07662687B2
公开(公告)日：2010-02-16
申请号：US12110849
申请日：2008-04-28
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。
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3.发明申请SEMICONDUCTOR MEMORY HAVING CHARGE TRAPPING MEMORY CELLS AND FABRICATION METHOD THEREOF 失效具有电荷捕获记忆体的半导体存储器及其制造方法公开(公告)号：US20090029512A1
公开(公告)日：2009-01-29
申请号：US12110849
申请日：2008-04-28
IPC分类号： H01L21/8247 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。
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4.发明授权Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US07365382B2
公开(公告)日：2008-04-29
申请号：US11067983
申请日：2005-02-28
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。
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公开(公告)号：US20060114724A1
公开(公告)日：2006-06-01
申请号：US11000335
申请日：2004-11-30
申请人： Stephan Riedel , Elard Kamienski , Norbert Schulze
发明人： Stephan Riedel , Elard Kamienski , Norbert Schulze
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/1203
摘要： A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.
摘要翻译： 非挥发性半导体存储器包括具有衬底区域，至少一个字线，布置在多个扇区中的多个非易失性存储单元的衬底，并且还包括第一掺杂类型的第一阱，电绝缘元件和开关 元素。 每个扇区包括通常布置在相应的第一阱中的多个非易失性存储单元。 所述至少一个字线电连接所述多个扇区中的一组扇区的存储单元。 第一个阱通过电绝缘元件从衬底区域和彼此分离。 每个第一阱连接到相应的开关元件，并且半导体存储器被构造成使得每个第一阱通过相应的开关元件可偏置到预定电位。 此外，提供了用于操作上述非易失性半导体存储器的方法。
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公开(公告)号：US20060054979A1
公开(公告)日：2006-03-16
申请号：US11010643
申请日：2004-12-13
申请人： Philipp Kratzert , Norbert Schulze , Juerg Haufe , Roland Haberkern , Stephan Riedel , Patrick Haibach
发明人： Philipp Kratzert , Norbert Schulze , Juerg Haufe , Roland Haberkern , Stephan Riedel , Patrick Haibach
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/66833
摘要： A method for fabricating a drain/source path is provided, in which essentially firstly a nitride layer is applied, on which a TEOS layer is then patterned. The patterning is effected in a simplified manner by virtue of the fact that the nitride layer acts as an etching stop layer during the etching away of the TEOS layer.
摘要翻译： 提供了一种用于制造漏极/源极路径的方法，其中基本上首先施加氮化物层，然后在其上构图TEOS层。 由于在TEOS层蚀刻期间氮化物层作为蚀刻停止层的事实，以简化的方式实现图案化。
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公开(公告)号：US07151697B2
公开(公告)日：2006-12-19
申请号：US11000335
申请日：2004-11-30
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/1203
摘要： A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.
摘要翻译： 非挥发性半导体存储器包括具有衬底区域，至少一个字线，布置在多个扇区中的多个非易失性存储单元的衬底，并且还包括第一掺杂类型的第一阱，电绝缘元件和开关 元素。 每个扇区包括通常布置在相应的第一阱中的多个非易失性存储器单元。 所述至少一个字线电连接所述多个扇区中的一组扇区的存储单元。 第一个阱通过电绝缘元件从衬底区域和彼此分离。 每个第一阱连接到相应的开关元件，并且半导体存储器被构造成使得每个第一阱通过相应的开关元件可偏置到预定电位。 此外，提供了用于操作上述非易失性半导体存储器的方法。
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公开(公告)号：US20050019914A1
公开(公告)日：2005-01-27
申请号：US10896660
申请日：2004-07-22
IPC分类号： C07K14/505 , C12N5/02 , C12N5/00
CPC分类号： C07K14/505
摘要： The invention relates to a process for producing erythropoietin (EPO) in which eukaryotic cells, which are suitable for expressing EPO, are adapted to SMIF7 medium in a suitable bioreactor, the resulting cells are transferred to a larger bioreactor and further expanded with SMIF7 medium and, while constantly bleeding and constantly perfusing, the expressed EPO is isolated from the larger bioreactor and purified.
摘要翻译： 本发明涉及一种生产促红细胞生成素（EPO）的方法，其中适合表达EPO的真核细胞在合适的生物反应器中适应于SMIF7培养基，将所得细胞转移到较大的生物反应器中并进一步用SMIF7培养基和 ，而不断出血和持续灌注，表达的EPO从较大的生物反应器中分离并纯化。
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