公开(公告)号：US6026479A

公开(公告)日：2000-02-15

申请号：US64701

申请日：1998-04-22

申请人： Joseph A. Fisher ,  Paolo Faraboschi ,  Paul G. Emerson ,  Prasad A. Raje

发明人： Joseph A. Fisher ,  Paolo Faraboschi ,  Paul G. Emerson ,  Prasad A. Raje

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30076 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3885

摘要： A CPU having a cluster VLIW architecture is shown which operates in both a high instruction level parallelism (ILP) mode and a low ILP mode. In high ILP mode, the CPU executes wide instruction words using all operational clusters of the CPU and all of a main instruction cache and main data cache of the CPU are accessible to a high ILP task. The CPU also includes a mini-instruction cache, a mini-instruction register and a mini-data cache which are inactive during high ILP mode. An instruction level controller in the CPU receives a low ILP signal, such as an interrupt or function call to a low ILP routine, and switches to low ILP mode. In low ILP mode, the main instruction cache and main data cache are deactivated to preserve their contents. At the same time, a predetermined cluster remains active while the remaining clusters are also deactivated. The low ILP task executes instructions from the mini-instruction cache which are input to the predetermined cluster through the mini-instruction register. The mini-data cache stores operands for the low ILP task. The separate mini-instruction cache and mini-data cache along with the use of only the predetermined cluster minimizes the pollution of the main instruction and data caches, as well as pollution of register files in the deactivated clusters, with regard to a task executing in high ILP mode.

摘要翻译： 示出了具有簇VLIW架构的CPU，其以高指令级并行（ILP）模式和低ILP模式操作。 在高ILP模式下，CPU使用CPU的所有操作群集执行宽指令字，并且高ILP任务可访问CPU的主指令高速缓存和主数据高速缓存。 CPU还包括微型指令高速缓存，微型指令寄存器和在高ILP模式期间不活动的微型数据高速缓存。 CPU中的指令级别控制器接收低ILP信号，例如对低ILP程序的中断或函数调用，并切换到低ILP模式。 在低ILP模式下，主指令高速缓存和主数据高速缓存被停用以保持其内容。 同时，预定的簇保持活动，而剩余的簇也被去激活。 低ILP任务执行通过迷你指令寄存器输入到预定簇的微指令高速缓存中的指令。 小数据高速缓存存储低ILP任务的操作数。 单独的迷你指令高速缓存和微型数据高速缓存以及仅使用预定的集群，最大限度地减少主指令和数据高速缓存的污染，以及对停用的集群中的寄存器文件的污染。 高ILP模式。

公开(公告)号：US5332933A

公开(公告)日：1994-07-26

申请号：US6418

申请日：1993-01-21

申请人： Prasad A. Raje

发明人： Prasad A. Raje

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/04 ,  H03K19/01 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/01

摘要： An optimum ratio relating the characteristic dimensions of the MOS pull-up and the MOS pull-down devices of a logic circuit with one or more bipolar devices connected to an output of the circuit. This optimum ratio substantially minimizes the propagation delay of the circuit. The first preferred embodiment is shown in a BiNMOS circuit, and the second preferred embodiment is shown in a BiCMOS circuit.

摘要翻译： 逻辑电路的MOS上拉和MOS下拉器件的特征尺寸与连接到电路的输出的一个或多个双极器件相关的最佳比率。 该最佳比例基本上使电路的传播延迟最小化。 第一优选实施例在BiNMOS电路中示出，并且第二优选实施例示于BiCMOS电路中。

公开(公告)号：US6105123A

公开(公告)日：2000-08-15

申请号：US38364

申请日：1998-03-10

申请人： Prasad A. Raje

发明人： Prasad A. Raje

IPC分类号： G06F9/30 ,  G11C7/10 ,  G06F9/00

CPC分类号： G06F9/30141 ,  G11C7/1039

摘要： A register file organization for a pipelined microprocessor is shown which includes a pipestage register interposed a global bit line and a register cell array of the register file in order to separate the delay associated with driving the global bit line, and devices attached to the global bit line, into a separate pipestage. Another register file organization is shown which includes a pipestage register that is interposed a register cell array and a decoder, which selects a register in the register cell array responsive to an instruction in an instruction register, to separate the decoder function and register cell array access times into different pipestages. The two approaches can be combined to separate the delay associated with the decoder, register cell array and global bit line into different pipestages in order to reduce the pipestage cycle time toward a fundamental minimum for pipelined computer architecture.

摘要翻译： 示出了用于流水线微处理器的寄存器文件组织，其包括插入全局位线和寄存器堆的寄存器单元阵列的分支寄存器，以便分离与驱动全局位线相关联的延迟，以及附加到全局位的器件 线，进入一个单独的管道。 示出了另一个寄存器文件组织，其包括插入了寄存器单元阵列和解码器的分支寄存器，其响应于指令寄存器中的指令来选择寄存器单元阵列中的寄存器，以分离解码器功能和寄存器单元阵列访问 进入不同的管道。 可以将两种方法组合以将与解码器，寄存器单元阵列和全局位线相关联的延迟分离成不同的管道，以便将流水线计算机体系结构的基础最小化的分支循环时间减少。

公开(公告)号：US5463326A

公开(公告)日：1995-10-31

申请号：US46540

申请日：1993-04-13

申请人： Prasad A. Raje

发明人： Prasad A. Raje

IPC分类号： H03K17/693 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K3/26

CPC分类号： H03K19/09429 ,  H03K19/018571 ,  H03K19/09448

摘要： A high frequency circuit using output drivers with tri-state sections. The plurality of output drivers are connected to an output transmission line. Each driver has a pull-up section, a pull-down section and a tri-state section. Each tri-state section has a low impedance and a high impedance state. Its low impedance state serves to match the impedance of the output transmission line. Its high impedance state isolates its driver from the output transmission line.

摘要翻译： 使用三态输出驱动器的高频电路。 多个输出驱动器连接到输出传输线。 每个驱动器都有一个上拉部分，一个下拉部分和一个三态部分。 每个三态部分具有低阻抗和高阻抗状态。 其低阻抗状态用于匹配输出传输线的阻抗。 其高阻抗状态将其驱动器与输出传输线隔离。

公开(公告)号：US5881260A

公开(公告)日：1999-03-09

申请号：US20474

申请日：1998-02-09

申请人： Prasad A. Raje ,  Stuart C. Siu

发明人： Prasad A. Raje ,  Stuart C. Siu

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3816 ,  G06F9/30152 ,  G06F9/30178 ,  G06F9/3885

摘要： An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register. An upper program count value is determined by loading a second shift register with the start bits, shifting the start bits in response to the lower program count value and detecting when only one instruction remains in the instruction buffer. When one instruction remains, the upper program count value is incremented and loaded into an upper program count register for output to the instruction cache in order to cause a fetch of another line of instructions and a `0` value is loaded into the lower program count register. Another embodiment of the present invention includes multiplexors for loading a branch address into the upper and lower program count registers in response to a branch control signal.

摘要翻译： 示出了用于解码处理器中的可变长度指令的装置和方法，其中来自指令高速缓存的可变长度指令的行被加载到指令缓冲器中，并且指示可变长度指令行中的指令的指令边界的起始位是 加载到起始位缓冲区。 第一移位寄存器加载起始位，并响应于也用于移位指令缓冲器的较低程序计数值移位。 通过检测第一寄存器中的起始位中下一个指令边界的位置来获得当前指令的长度。 当前指令的长度被添加到较低程序计数值的当前值，以便获得下载程序计数寄存器中的较低程序计数的下一个顺序值。 通过加载具有起始位的第二移位寄存器来确定较高的编程计数值，根据较低的程序计数值移位起始位，并检测何时只有一条指令留在指令缓冲器中。 当一个指令仍然存在时，上位程序计数值递增并加载到上位程序计数寄存器中，以输出到指令高速缓存，以便获取另一行指令，并将“0”值加载到较低程序计数 寄存器。 本发明的另一实施例包括用于响应于分支控制信号将分支地址加载到上和下程序计数寄存器中的多路复用器。