公开(公告)号：US5717885A

公开(公告)日：1998-02-10

申请号：US741749

申请日：1996-11-05

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a lower portion. The upper portion is always compared to an upper virtual page number entry in a first content addressable memory while only certain bits of lower portion are selectively compared to a corresponding number of bits in a lower virtual page number entry in a second content addressable memory. The number of bits compared in the second content addressable memory is determined by the specified size of the physical page. The TLB includes a page size memory having a plurality of page size entries wherein the certain number of bits for each of the lower virtual page entries is specified by a corresponding page size entry. Associated with each bit in the lower virtual page number entries is an enable transistor for selectively enabling the comparison of that bit in the lower virtual page number entry. The enable gate includes a control input coupled to a corresponding bit in a corresponding page size entry, the enable transistor selectively enabling the single bit comparison when the corresponding bit in the page size entry is set to an enable state and selectively disabling the comparison when the corresponding bit in the page size entry is set to a disable state.

摘要翻译： 用于将可变页大小的虚拟页号翻译成物理页号的翻译后备缓冲器（TLB）。 TLB将虚拟页码分成上部和下部。 上部部分总是与第一内容可寻址存储器中的上虚拟页号码条目进行比较，而仅将下部分的某些比特选择性地与第二内容可寻址存储器中的较低虚拟页号码条目中的相应位数比较。 在第二内容可寻址存储器中比较的比特数由物理页面的指定大小确定。 TLB包括具有多个页面大小条目的页面大小存储器，其中每个较低虚拟页面条目的特定数量的位由相应的页面大小条目指定。 与较低虚拟页号码条目中的每个位相关联的是使能晶体管，用于选择性地启用较低虚拟页码条目中该位的比较。 使能栅极包括耦合到相应页面大小条目中的对应位的控制输入，当页面大小条目中的相应位被设置为使能状态时，使能晶体管有选择地启用单个位比较，并且当 页面大小条目中的相应位被设置为禁用状态。

公开(公告)号：US20180344687A1

公开(公告)日：2018-12-06

申请号：US15993576

申请日：2018-05-30

申请人： Paul G. Emerson

发明人： Paul G. Emerson

IPC分类号： A61K31/353 ,  A61K31/381 ,  A61K31/198 ,  A61P5/00 ,  A61P25/02 ,  A61P25/00 ,  A61P9/12 ,  A61P25/30 ,  A61P25/28

CPC分类号： A61K31/353 ,  A61K31/198 ,  A61K31/381 ,  A61P5/00 ,  A61P9/12 ,  A61P25/00 ,  A61P25/02 ,  A61P25/28 ,  A61P25/30

摘要： The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

公开(公告)号：US5649154A

公开(公告)日：1997-07-15

申请号：US547047

申请日：1995-10-23

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0862

摘要： A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output data bitlines, sense amplifiers, and bus drivers as the direct mapped cache. In a first machine cycle, input address tags are simultaneously compared to tag bits in the primary cache and the secondary cache. If the comparison results in a miss in the primary cache and a hit in the secondary cache, the secondary cache data is fed to the microprocessor in the next machine cycle, precluding the need for a main memory access. Thus, allowing data to be read directly from the secondary cache without using an extra machine cycle to load it first into the direct cache. The secondary cache comprises a miss cache which is loaded from main memory with data missing from the primary cache in the first machine cycle. Alternatively, the secondary cache comprises a victim cache which is loaded with a line of the primary cache which is replaced after loading missed data from main memory.

摘要翻译： 一种高速缓冲存储器系统，其具有与直接映射的一级高速缓存集成的二级缓存，其中单个结构优选地构造在VLSI芯片上。 二级缓存使用相同的输出数据位线，读出放大器和总线驱动器作为直接映射缓存。 在第一个机器周期中，输入地址标签与主缓存和二级缓存中的标签位同时进行比较。 如果比较导致主缓存中的未命中和次级高速缓存中的命中，则次级高速缓存数据在下一个机器周期中被馈送到微处理器，排除了对主存储器访问的需要。 因此，允许直接从二级缓存读取数据，而不用额外的机器周期将其首先加载到直接高速缓存中。 次级高速缓存包括从主存储器加载的未命中高速缓存，其中在第一机器周期中从主缓存中缺少数据。 或者，辅助高速缓存包括被加载有主缓存的行的受害缓存，在从主存储器加载丢失的数据之后被替换。

公开(公告)号：US6026479A

公开(公告)日：2000-02-15

申请号：US64701

申请日：1998-04-22

申请人： Joseph A. Fisher ,  Paolo Faraboschi ,  Paul G. Emerson ,  Prasad A. Raje

发明人： Joseph A. Fisher ,  Paolo Faraboschi ,  Paul G. Emerson ,  Prasad A. Raje

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30076 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3885

摘要： A CPU having a cluster VLIW architecture is shown which operates in both a high instruction level parallelism (ILP) mode and a low ILP mode. In high ILP mode, the CPU executes wide instruction words using all operational clusters of the CPU and all of a main instruction cache and main data cache of the CPU are accessible to a high ILP task. The CPU also includes a mini-instruction cache, a mini-instruction register and a mini-data cache which are inactive during high ILP mode. An instruction level controller in the CPU receives a low ILP signal, such as an interrupt or function call to a low ILP routine, and switches to low ILP mode. In low ILP mode, the main instruction cache and main data cache are deactivated to preserve their contents. At the same time, a predetermined cluster remains active while the remaining clusters are also deactivated. The low ILP task executes instructions from the mini-instruction cache which are input to the predetermined cluster through the mini-instruction register. The mini-data cache stores operands for the low ILP task. The separate mini-instruction cache and mini-data cache along with the use of only the predetermined cluster minimizes the pollution of the main instruction and data caches, as well as pollution of register files in the deactivated clusters, with regard to a task executing in high ILP mode.

摘要翻译： 示出了具有簇VLIW架构的CPU，其以高指令级并行（ILP）模式和低ILP模式操作。 在高ILP模式下，CPU使用CPU的所有操作群集执行宽指令字，并且高ILP任务可访问CPU的主指令高速缓存和主数据高速缓存。 CPU还包括微型指令高速缓存，微型指令寄存器和在高ILP模式期间不活动的微型数据高速缓存。 CPU中的指令级别控制器接收低ILP信号，例如对低ILP程序的中断或函数调用，并切换到低ILP模式。 在低ILP模式下，主指令高速缓存和主数据高速缓存被停用以保持其内容。 同时，预定的簇保持活动，而剩余的簇也被去激活。 低ILP任务执行通过迷你指令寄存器输入到预定簇的微指令高速缓存中的指令。 小数据高速缓存存储低ILP任务的操作数。 单独的迷你指令高速缓存和微型数据高速缓存以及仅使用预定的集群，最大限度地减少主指令和数据高速缓存的污染，以及对停用的集群中的寄存器文件的污染。 高ILP模式。

公开(公告)号：US5513363A

公开(公告)日：1996-04-30

申请号：US293862

申请日：1994-08-22

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F9/30 ,  G06F9/38 ,  G11C8/16 ,  G06F9/00

CPC分类号： G06F9/30141 ,  G06F9/3012 ,  G06F9/3875 ,  G11C8/16

摘要： A scalable register file including first and second micro-register files organized in a pipelined fashion to minimize the access time of the register file where there are a large number of registers or multiple functional units. Interposed between the first and second micro-register files are a first plurality of pipeline registers for storing the register contents fetched from the first micro-register file during a first pipeline cycle. A second plurality of pipeline registers are coupled to the second micro-register files for storing the register contents fetched from the second micro-register file during a second pipeline stage and those registers being stored in the first plurality of pipeline registers. The first plurality of pipeline registers are coupled to the bit lines of the second micro-register file. Enable logic is coupled to each of the first plurality pipeline registers to selectively present the contents of the first plurality of pipeline register to the second plurality of pipeline registers if there were contents stored in a first pipeline register during the first pipeline cycle. Alternatively, a multiplexer can be used to present the register contents stored in the first plurality of pipeline registers to the second plurality of pipeline registers.

摘要翻译： 一种可扩展的寄存器文件，包括以流水线方式组织的第一和第二微寄存器文件，以最小化寄存器文件的存储时间，其中存在大量寄存器或多个功能单元。 介于第一和第二微寄存器文件之间的是第一多个流水线寄存器，用于存储在第一流水线循环期间从第一微寄存器文件获取的寄存器内容。 第二多个流水线寄存器耦合到第二微寄存器文件，用于存储在第二流水线级期间从第二微寄存器文件获取的寄存器内容，并且这些寄存器被存储在第一多个流水线寄存器中。 第一组多个流水线寄存器耦合到第二微寄存器堆的位线。 如果在第一流水线循环期间存在第一流水线寄存器中的内容，则启用逻辑被耦合到第一多个流水线寄存器中的每一个，以便有选择地将第一多个流水线寄存器的内容呈现给第二多个流水线寄存器。 或者，可以使用多路复用器将存储在第一多个流水线寄存器中的寄存器内容呈现给第二多个流水线寄存器。

公开(公告)号：US10588890B2

公开(公告)日：2020-03-17

申请号：US15993576

申请日：2018-05-30

申请人： Paul G. Emerson

发明人： Paul G. Emerson

IPC分类号： A61K31/353 ,  A61K31/381 ,  A61K31/198 ,  A61P5/00 ,  A61P25/28 ,  A61P25/00 ,  A61P9/12 ,  A61P25/30 ,  A61P25/02

摘要： The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

公开(公告)号：US5590087A

公开(公告)日：1996-12-31

申请号：US533133

申请日：1995-09-25

申请人： Shine Chung ,  Paul G. Emerson

发明人： Shine Chung ,  Paul G. Emerson

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/34 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/16

摘要： An improved memory type multi-ported data storage device is disclosed. The storage device operates to overcome the cell stability problems associated with the prior art by unidirectionally isolating memory cells of the multi-ported data storage device from read ports of the multi-ported data storage device. The unidirectional isolation operates to prevent external signals from the read ports and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed.

摘要翻译： 公开了一种改进的存储器型多端口数据存储设备。 存储设备通过将多端口数据存储设备的存储器单元与多端口数据存储设备的读端口单向隔离来操作以克服与现有技术相关联的单元稳定性问题。 单向隔离操作以防止来自读端口的外部信号和从存储单元中存储的影响数据读取端口负载，但是继续允许存储单元由与其相关联的读端口读取。 改进的多端口数据存储设备不仅允许通过大量读取端口同时访问其存储器单元，而不用担心单元稳定性将导致存储器单元的损坏，而且仅需要最小量的附加管芯区域。 此外，访问时间与同时访问的端口数无关。