公开(公告)号：US06798019B2

公开(公告)日：2004-09-28

申请号：US10055211

申请日：2002-01-23

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

IPC分类号： H01L2973

CPC分类号： H01L29/0696 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/7395 ,  H01L29/7397

摘要： An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.

摘要翻译： IGBT具有沿着基带3的长度连续或分段的源极条2a，2b的条纹单元。相反的条由N +接触区域20周期性地连接在一起，以沿着源极条2a，2b的宽度提供沟道电阻 。 对于连续条纹，两个顺序接触区域20a，20b之间的电阻在中间是最大的，并且电流集中在源极接触区域20附近。触点20之间的间隔越宽，两个N +触点20之间的中点的电阻降低越大 。

公开(公告)号：US06777747B2

公开(公告)日：2004-08-17

申请号：US10050976

申请日：2002-01-18

申请人： Joseph A. Yedinak ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

发明人： Joseph A. Yedinak ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

IPC分类号： H01L2976

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/7395

摘要： An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

摘要翻译： IGBT具有增加掺杂的厚缓冲区，以改善自感感开关和器件制造。 平面或沟槽栅极IGBT具有超过25微米厚的缓冲层。 缓冲层被掺杂得足够高，使得其载流子比少数载流子更多，特别是在N缓冲区和N漂移区之间的转变。

公开(公告)号：US4146826A

公开(公告)日：1979-03-27

申请号：US742068

申请日：1976-11-15

申请人： Jack E. Wojslawowicz

发明人： Jack E. Wojslawowicz

IPC分类号： E05F15/16 ,  H02P7/00 ,  H02P1/08

CPC分类号： E05F15/695 ,  H02P7/05 ,  E05Y2900/55 ,  Y10T307/76

摘要： Gate-turn-off silicon controlled rectifiers (GTO's) are selectively rendered conductive to control the direction of rotation of a bi-directional motor. To this end a digital logic network is responsive to either one or both of a pair of remotely located switches being operated to either a first or a second condition, for controlling a transistorized gate signal generating network to apply an operating voltage to the gate electrode of the appropriate one(s) of the GTO's. The gate signal generating network includes circuitry for grounding the gates of the GTO's, turning them off if on and thereby inhibiting operation of the motor, whenever either of two operating conditions obtains. The first of these conditions occur when the switches are operated sequentially to be concurrently one in the first condition and the other in the second condition, and the second of these conditions is when one of the switches is returned from the first or second condition to a neutral condition with the other switch being in the neutral condition.