公开(公告)号：US20090323879A1

公开(公告)日：2009-12-31

申请号：US12105897

申请日：2008-04-18

申请人： Joseph Caltagirone ,  James Dewey Parker

发明人： Joseph Caltagirone ,  James Dewey Parker

IPC分类号： H04L7/00

CPC分类号： G06F13/4291

摘要： Methods and apparatus are provided for a system for aligning data. The apparatus comprises a demultiplexing component adapted to bifurcate a double data rate (DDR) data stream into a first single data rate (SDR) data stream and a second SDR data stream, a bit detection component coupled to the demultiplexing component and adapted to compare bit values between the first and second SDR data streams and generate a first signal in response to detection of a predetermined arrangement of bits, a delay component adapted to receive the DDR data stream and perform a delay operation on the DDR data stream to create a delayed data stream, and a data alignment component coupled to the demultiplexing component, the delay component, and to the bit detection component, the data alignment component being adapted to place the delayed data stream in alignment in response to the first signal.

摘要翻译： 为数据对齐的系统提供了方法和装置。 所述装置包括解复用部件，其适于将双数据速率（DDR）数据流分分成第一单数据速率（SDR）数据流和第二SDR数据流，耦合到解复用部件的比特检测组件，并且适于比较比特 第一和第二SDR数据流之间的值，并且响应于预定比特排列的检测而生成第一信号，延迟组件，适于接收DDR数据流，并对DDR数据流执行延迟操作以创建延迟数据 流，以及耦合到解复用部件，延迟部件和位检测部件的数据对准部件，数据对准部件适于响应于第一信号使延迟的数据流对准。

公开(公告)号：US20090310433A1

公开(公告)日：2009-12-17

申请号：US12138066

申请日：2008-06-12

申请人： Joseph Caltagirone ,  James Dewey Parker

发明人： Joseph Caltagirone ,  James Dewey Parker

IPC分类号： G11C8/16

CPC分类号： G06F13/4291

摘要： A system for aligning data is provided. The system comprises a demultiplexing component adapted to bifurcate a double data rate (DDR) data stream into first and second single data rate (SDR) data streams, a delay architecture adapted to generate delayed SDR data streams from the SDR data streams, a logic circuit adapted to analyze the SDR data streams and delayed SDR data streams to detect a predetermined bit pattern conveyed in the DDR data stream and to indicate detection of the predetermined bit pattern, and a data aligning component adapted to determine the number of intervening bits between occurrences of the predetermined bit pattern and to frame the intervening bits, thereby producing aligned data.

摘要翻译： 提供了一种用于对齐数据的系统。 所述系统包括解复用部件，其适于将双数据速率（DDR）数据流分成第一和第二单数据速率（SDR）数据流，适于从SDR数据流生成延迟的SDR数据流的延迟架构，逻辑电路 适于分析SDR数据流和延迟的SDR数据流以检测在DDR数据流中传送的预定位模式并指示对预定位模式的检测，以及数据对准组件，适于确定出现之间的中间位数 预定的位模式并且对中间位进行帧化，由此产生对准的数据。

公开(公告)号：US20090323730A1

公开(公告)日：2009-12-31

申请号：US12105845

申请日：2008-04-18

申请人： Joseph Caltagirone ,  James Dewey Parker ,  Brett Oliver

发明人： Joseph Caltagirone ,  James Dewey Parker ,  Brett Oliver

IPC分类号： H04J3/04

CPC分类号： G06F13/4291 ,  H04L25/14 ,  H04L25/4904

摘要： Methods and apparatus are provided for a system for aligning data. The apparatus comprises a demultiplexing component adapted to bifurcate a DDR data stream into first and second SDR data streams, a sequence detection component coupled to the demultiplexing component and adapted to detect a pattern of sequential bit values in the first SDR data stream, and a data alignment component coupled to the demultiplexing component and to the sequence detection component, the data alignment component adapted to place the second SDR data stream in alignment with the pattern of sequential bit values in the first SDR data stream.

摘要翻译： 为数据对齐的系统提供了方法和装置。 该装置包括：解复用部件，适于将DDR数据流分为第一和第二SDR数据流;序列检测部件，耦合到解复用部件，并适于检测第一SDR数据流中的连续位值的模式;以及数据 对齐分量耦合到解复用部件和序列检测部件，数据对准部件适于将第二SDR数据流与第一SDR数据流中的顺序位值的模式对准。

公开(公告)号：US20090310626A1

公开(公告)日：2009-12-17

申请号：US12139278

申请日：2008-06-13

申请人： Joseph Caltagirone ,  James Dewey Parker

发明人： Joseph Caltagirone ,  James Dewey Parker

IPC分类号： H04J3/06

CPC分类号： G06F13/4278 ,  H04L7/0338 ,  H04L7/04

摘要： Methods and apparatus are provided for a system for aligning data. The apparatus comprises a data processing component adapted to produce a plurality of processed data streams delayed by a successively increasing number of clock cycles, a plurality of sequence detection components coupled to the data processing component, each of the plurality of sequence detection components adapted to inspect its input data stream for a predetermined sequence of bits, and a data selecting component adapted to receive the plurality of processed data streams, to select one of the plurality of processed data streams in response to receiving an indicator from a corresponding sequence detection component.

摘要翻译： 为数据对齐的系统提供了方法和装置。 该装置包括一个数据处理部件，适用于产生延迟了连续增加的时钟周期数量的多个经处理数据流，耦合到数据处理部件的多个序列检测部件，多个序列检测部件中的每一个适于检查 其用于预定比特序列的输入数据流以及适于接收多个经处理的数据流的数据选择组件，以响应于从相应的序列检测组件接收到指示符来选择所述多个经处理的数据流中的一个。