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公开(公告)号：US07028106B2
公开(公告)日：2006-04-11
申请号：US10728480
申请日：2003-12-05
IPC分类号： G06F13/00
CPC分类号： G06F13/404 , G06F13/4045
摘要： A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, wherein each interface is allocated to a respective set of routing information entries. Mapping logic remaps unused routing information of one of the interfaces to one or more other interfaces to expand capacity of the one or more other interfaces.
摘要翻译： 一种系统包括具有耦合到一个或多个外围设备和扩展器的接口的外围设备和扩展器。 扩展器具有存储，用于存储包含用于将扩展器接收的请求路由到其中一个接口的路由信息的条目，其中每个接口被分配给相应的一组路由信息条目。 映射逻辑将其中一个接口的未使用路由信息重新映射到一个或多个其他接口，以扩展一个或多个其他接口的容量。
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2.发明授权公开(公告)号：US07340551B2
公开(公告)日：2008-03-04
申请号：US11274607
申请日：2005-11-15
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F3/0601 , G06F2003/0692
摘要： A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from or provided to the storage drive.
摘要翻译： 桥接器包括到多个主机的接口，到单端口存储驱动器和仲裁逻辑的接口。 仲裁逻辑控制和允许主机同时访问单端口存储驱动器，使得该桥不需要存储从存储驱动器接收或提供给存储驱动器的读或写数据。
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3.发明授权Dynamic remapping of address registers for address translation between multiple busses 有权地址寄存器的动态重映射用于多个总线之间的地址转换公开(公告)号：US06581130B1
公开(公告)日：2003-06-17
申请号：US09542420
申请日：2000-04-04
IPC分类号： G06F1336
CPC分类号： G06F12/0284 , G06F12/0692 , G06F13/404
摘要： Address translation between various peripheral bus interfaces is provided through a bus interface device. Specifically, the bus interface device translates incoming transactions from a source bus interface to a different address or location within a destination bus interface. Flexibility for communications between multiple bus interfaces having different, possibly conflicting, address spaces is ensured by allowing the internal translation registers to be dynamically reprogrammed. Reprogramming of the translation registers may occur during runtime bus operations. These registers define translation windows within which a transaction will be claimed and translated to the destination bus interface. Translation is accomplished using the translation registers to identify portions of the incoming received address which should not be translated because those portions contain the information to be communicated. At the same time, portions identifying only the location of the information are translated to identify a different location within the destination address space.
摘要翻译： 通过总线接口设备提供各种外设总线接口之间的地址转换。 具体地，总线接口设备将来自源总线接口的传入事务转换为目的地总线接口内的不同地址或位置。 通过允许内部转换寄存器被动态重新编程，确保具有不同的，可能冲突的地址空间的多个总线接口之间的通信的灵活性。 翻译寄存器的重新编程可能在运行时总线操作期间发生。 这些寄存器定义了翻译窗口，在该窗口中，将要求转换事务并将其转换为目标总线接口。 使用翻译寄存器来完成翻译，以识别不应翻译的传入接收地址的部分，因为这些部分包含要传达的信息。 同时，仅识别信息的位置的部分被转换以标识目的地址空间内的不同位置。
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4.发明授权Dynamic routing of data across multiple data paths from a source controller to a destination controller 有权从源控制器到目标控制器的多个数据路径的数据动态路由公开(公告)号：US06675253B1
公开(公告)日：2004-01-06
申请号：US09542309
申请日：2000-04-04
IPC分类号： G06F1300
CPC分类号： G06F3/0613 , G06F3/0635 , G06F3/0689 , G06F12/0866 , G06F13/4022
摘要： A drive array controller or other data handling system supports dynamic data routing across multiple data paths between a source controller and a destination controller. Each data path between the source controller and the data controller can include a cache memory. Based on detection of a cache address, the data path with the cache memory corresponding to the cache address is selected. Data transfer to a single destination controller can be alternated between different data paths based on detection of different cache addresses. Each data path can include a plurality of bus/memory interface devices and a peripheral bus such as a peripheral component interconnect (PCI) bus. As an alternative to dynamic data routing based on addressing, data routing can be based on command type.
摘要翻译： 驱动器阵列控制器或其他数据处理系统支持在源控制器和目标控制器之间的多个数据路径上的动态数据路由。 源控制器和数据控制器之间的每个数据路径可以包括高速缓冲存储器。 基于高速缓存地址的检测，选择与高速缓存地址对应的高速缓冲存储器的数据路径。 基于检测不同的缓存地址，可以在不同数据路径之间交替传送到单个目标控制器。 每个数据路径可以包括多个总线/存储器接口设备和诸如外围组件互连（PCI）总线的外围总线。 作为基于寻址的动态数据路由的替代，数据路由可以基于命令类型。
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