公开(公告)号：US20110316061A1

公开(公告)日：2011-12-29

申请号：US12822492

申请日：2010-06-24

申请人： Joseph ERVIN ,  Jeffrey B. JOHNSON ,  Kevin MCSTAY ,  Paul C. PARRIES ,  Chengwen PEI ,  Geng WANG ,  Yanli ZHANG

发明人： Joseph ERVIN ,  Jeffrey B. JOHNSON ,  Kevin MCSTAY ,  Paul C. PARRIES ,  Chengwen PEI ,  Geng WANG ,  Yanli ZHANG

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76237 ,  H01L27/10847 ,  H01L27/1203

摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

摘要翻译： 半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。 一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。 掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

公开(公告)号：US20120012971A1

公开(公告)日：2012-01-19

申请号：US12838515

申请日：2010-07-19

申请人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

发明人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

IPC分类号： H01L29/06 ,  H01L29/92 ,  G06F17/50 ,  H01L21/02

CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

公开(公告)号：US20120267754A1

公开(公告)日：2012-10-25

申请号：US13533099

申请日：2012-06-26

申请人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

发明人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

IPC分类号： H01L29/92

CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。