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    FET structures with trench implantation to improve back channel leakage and body resistance
    2.
    发明授权
    FET structures with trench implantation to improve back channel leakage and body resistance 有权
    具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻

    公开(公告)号：US08809953B2

    公开(公告)日：2014-08-19

    申请号：US13426547

    申请日：2012-03-21

    申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

    摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

    POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH
    4.
    发明申请
    POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH 有权
    深层TRENCH中的多晶硅/金属接触电阻

    公开(公告)号：US20130134491A1

    公开(公告)日：2013-05-30

    申请号：US13307874

    申请日：2011-11-30

    申请人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L27/108 ,  H01L21/02

    CPC分类号： H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

    摘要翻译： 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

    Method and apparatus for adaptive black frame insertion
    5.
    发明授权
    Method and apparatus for adaptive black frame insertion 有权
    自适应黑框插入的方法和装置

    公开(公告)号：US08358260B2

    公开(公告)日：2013-01-22

    申请号：US12384500

    申请日：2009-04-06

    申请人： Akihiro Takagi ,  Cheng-Shih Chin ,  Yanli Zhang ,  Maximino Vasquez

    发明人： Akihiro Takagi ,  Cheng-Shih Chin ,  Yanli Zhang ,  Maximino Vasquez

    IPC分类号： G09G3/36

    CPC分类号： G09G3/36 ,  G09G3/3611 ,  G09G3/3614 ,  G09G2310/061 ,  G09G2320/103 ,  G09G2340/0435

    摘要： A display device may include a flat panel display, and a controller coupled to the flat panel display. The controller may be configured to determine an operating mode for the flat panel display among a plurality of operating modes including at least a first operating mode and a second operating mode. In the first operating mode, the controller may set the flat panel display to utilize a first frame rate and a first inversion mode to save power. In the second operating mode, the controller may set the flat panel display to utilize a second frame rate, a second inversion mode, and a black frame insertion to improve image quality. The second frame rate may be faster than the first frame rate. The second inversion mode and black frame insertion may be mutually configured to maintain a DC balanced operation of the flat panel display.

    摘要翻译： 显示装置可以包括平板显示器和耦合到平板显示器的控制器。 控制器可以被配置为在包括至少第一操作模式和第二操作模式的多个操作模式中确定平板显示器的操作模式。 在第一操作模式中，控制器可以设置平板显示器以利用第一帧速率和第一反转模式来节省功率。 在第二操作模式中，控制器可以将平板显示器设置为利用第二帧速率，第二反转模式和黑帧插入以提高图像质量。 第二帧速率可以比第一帧速率更快。 第二反转模式和黑框插入可以相互配置以保持平板显示器的直流平衡操作。

    SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF
    10.
    发明申请
    SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF 失效
    自对准结构及其设计结构

    公开(公告)号：US20130168822A1

    公开(公告)日：2013-07-04

    申请号：US13343287

    申请日：2012-01-04

    申请人： William F. CLARK, JR. ,  John J. PEKARIK ,  Yun SHI ,  Yanli ZHANG

    发明人： William F. CLARK, JR. ,  John J. PEKARIK ,  Yun SHI ,  Yanli ZHANG

    IPC分类号： H01L29/732 ,  G06F17/50 ,  H01L21/331

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/732

    摘要： Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.

    摘要翻译： 垂直双极结结构，制造方法和设计结构。 该方法包括在芯片的第一区域中形成用于双极结型晶体管（BJT）的一个或多个牺牲结构。 该方法包括在一个或多个牺牲结构上形成掩模。 该方法还包括蚀刻掩模中与该一个或多个牺牲结构对准的开口。 该方法包括通过该开口形成沟槽并延伸到一个或多个牺牲结构下方的扩散区域中。 该方法包括通过在沟槽中沉积与扩散区接触的外延材料来形成BJT的基极区域。 该方法包括通过在沟槽内的基极区域上沉积第二外延材料来形成发射极接触。 用于发射极区域的外延材料具有与基极区域的外延材料相反的掺杂剂类型。