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    Low jitter differential amplifier with negative hysteresis
    1.
    发明授权
    Low jitter differential amplifier with negative hysteresis 失效
    具有负滞后的低抖动差分放大器

    公开(公告)号：US06377108B1

    公开(公告)日：2002-04-23

    申请号：US09649257

    申请日：2000-08-28

    申请人： Joseph T. Kennedy ,  Stephen R. Mooney ,  Aaron K. Martin ,  Rajendran Nair

    发明人： Joseph T. Kennedy ,  Stephen R. Mooney ,  Aaron K. Martin ,  Rajendran Nair

    IPC分类号： H03K1776

    CPC分类号： H03K5/088

    摘要： A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.

    摘要翻译： 提供了一个差分放大器，通过自动参考电压调整结合了负滞后。 延迟的输出信号被路由到开关或多路复用器，其用于选择两个参考电压电平之一，产生负的滞后。 延迟的输出信号由一系列逆变器延迟，这防止本发明的某些实施例在某些情况下振荡。 两个参考电压电平被选择为接近相应的数据信号输入高和低信号电压电平，但远离这些电平，以免受噪声或其他干扰的不利影响。

    Complementary input self-biased differential amplifier with gain compensation
    2.
    发明授权
    Complementary input self-biased differential amplifier with gain compensation 有权
    具有增益补偿的互补输入自偏置差分放大器

    公开(公告)号：US06304141B1

    公开(公告)日：2001-10-16

    申请号：US09609495

    申请日：2000-06-30

    申请人： Joseph T. Kennedy ,  Stephen R. Mooney ,  Aaron K. Martin ,  Rajendran Nair

    发明人： Joseph T. Kennedy ,  Stephen R. Mooney ,  Aaron K. Martin ,  Rajendran Nair

    IPC分类号： H03F345

    CPC分类号： H03F3/45233 ,  H03F3/3028 ,  H03F3/45237 ,  H03F2203/45371 ,  H03F2203/45451 ,  H03F2203/45454 ,  H03F2203/45708

    摘要： A complementary input self-biased differential amplifier includes gain compensation devices. The gain compensation devices are in parallel with input transistors and are biased by a self-bias node. The gain control devices serve to keep current flowing in load devices when operating at common-mode extremes, thereby limiting the reduction in amplifier output impedance and limiting the corresponding reduction in differential-mode gain at common-mode extremes. The gain control devices also serve to reduce input stage transconductance near the center of the common-mode input voltage swing, thereby reducing differential-mode gain near the center of the swing, and reducing gain variations across the input common-mode range. The differential amplifier can include multiple input legs on either side of an input stage. Multiple legs allow multiple reference voltages to be compared to a data signal. A bidirectional data link utilizes the multiple reference inputs to remove an ambiguity created by the bidirectional data link.

    摘要翻译： 互补输入自偏置差分放大器包括增益补偿装置。 增益补偿装置与输入晶体管并联并由自偏压节点偏置。 增益控制装置用于在共模极端工作时保持电流在负载装置中流动，从而限制了放大器输出阻抗的减小，并限制了共模极限下差分模式增益的相应降低。 增益控制装置还用于减小共模输入电压摆幅中心附近的输入级跨导，从而减小摆幅中心附近的差模增益，并减少输入共模范围内的增益变化。 差分放大器可以包括输入级两侧的多个输入支路。 多个支路允许将多个参考电压与数据信号进行比较。 双向数据链路利用多个参考输入来消除由双向数据链路创建的歧义。

    On-chip observability buffer to observer bus traffic
    5.
    发明授权
    On-chip observability buffer to observer bus traffic 失效
    观察员总线流量的片上可观察性缓冲区

    公开(公告)号：US07171510B2

    公开(公告)日：2007-01-30

    申请号：US09752880

    申请日：2000-12-28

    申请人： Matthew B. Haycock ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Matthew B. Haycock ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： G06F13/36 ,  G06F13/14 ,  G06F11/00 ,  G01R31/00 ,  G01R31/14

    CPC分类号： G06F11/221

    摘要： The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.

    摘要翻译： 本发明在一个实施例中提供了一种用于非干涉地观察，回送和读取由总线和无线通信之一发送的信号而不干扰总线的电气特性而不增加总线等待时间并且不增加信号不连续性的装置，方法和装置 。 在一方面，具有触发器的缓冲器与连接到存储器总线的部件耦合，缓冲器将信号回送到可观测端口，并且诊断装置读取回送信号。 一方面，总线是具有三元逻辑电平的同时双向（SBD）总线之一，单端总线，差分总线，光耦合总线，芯片组总线，前端总线，输入/输出（ I / O）总线，外设组件接口（PCI）总线和工业标准架构（ISA）总线。 在一个方面，缓冲器回波频率在500MHz之间的总线信号。 和5 GHz。 在一方面，缓冲器响应具有至少5GHz频率的总线信号。

    Transition reduction encoder using current and last bit sets
    6.
    发明授权
    Transition reduction encoder using current and last bit sets 失效
    使用当前位和最后位的转换减速编码器

    公开(公告)号：US06538584B2

    公开(公告)日：2003-03-25

    申请号：US09752883

    申请日：2000-12-28

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03M700

    CPC分类号： G11C7/10

    摘要： In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

    摘要翻译： 在一些实施例中，本发明涉及包括第一组导体的电路，以承载当前位组和最后位组电路以保持并提供最后位组。 电路还包括耦合到互连导体的驱动器以提供从驱动器到互连导体的信号，以及用于接收最后位组和当前位组的编码器，并确定是提供当前位组还是当前位的编码版本 设置为司机。

    Rail-to-rail input clocked amplifier
    7.
    发明授权
    Rail-to-rail input clocked amplifier 失效
    轨至轨输入时钟放大器

    公开(公告)号：US06441649B1

    公开(公告)日：2002-08-27

    申请号：US09752647

    申请日：2000-12-29

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： G01R1900

    CPC分类号： H03K3/356191 ,  H03K3/35613

    摘要： The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

    摘要翻译： 本发明提供了一种用于捕获数据的装置，方法和装置。 在一方面，提供差分和互补输入折叠共源共栅时钟放大器。 在一方面，本发明提供轨至轨输入共模电压范围。 在一方面，本发明提供了一种建立/保持时间窗口，其小于常规时钟放大器和具有单独放大器和锁存器的常规输入放大器的建立/保持时间窗口。 在一方面，与传统的时钟感测放大器相比，本发明提供了高共模抑制。

    Simultaneous transmission and reception of signals in different frequency bands over a bus line
    8.
    发明授权
    Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
    在总线上同时发送和接收不同频段的信号

    公开(公告)号：US07177288B2

    公开(公告)日：2007-02-13

    申请号：US09998008

    申请日：2001-11-28

    申请人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    发明人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    IPC分类号： H04L5/14

    CPC分类号： H04L5/1423

    摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

    摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。

    Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference
    9.
    发明授权
    Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference 有权
    使用从动到闭环定时参考的匹配的受控延迟元件来最小化抖动的方法

    公开(公告)号：US06774686B2

    公开(公告)日：2004-08-10

    申请号：US09968460

    申请日：2001-09-28

    申请人： Joseph T. Kennedy ,  Bryan K. Casper ,  Stephen R. Mooney ,  Aaron K. Martin

    发明人： Joseph T. Kennedy ,  Bryan K. Casper ,  Stephen R. Mooney ,  Aaron K. Martin

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  H03L7/0812

    摘要： A method for minimizing jitter using substantially matched, controlled, delay elements is disclosed. The method includes generating an internal loop-timing reference, and controlling elements outside of the loop with the internal loop-timing reference generated. In one embodiment the outside elements are substantially identical to those internal to the closed-loop. Controlled delay elements for preconditioning and distributing closed-loop inputs and outputs, using the same control reference used by internal loop elements are disclosed.

    摘要翻译： 公开了一种使用基本匹配的受控延迟元件来最小化抖动的方法。 该方法包括生成内部循环定时参考，以及生成内部循环定时参考，控制环外的元素。 在一个实施例中，外部元件与闭环内部元件基本相同。 公开了用于预调节和分配闭环输入和输出的受控延迟元件，使用与内部环路元件相同的控制参考。

    Using a timing strobe for synchronization and validation in a digital logic device
    10.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。