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1.发明授权Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权金属门功能工程技术可实现多个阈值电压FINFET器件公开(公告)号：US08669167B1
公开(公告)日：2014-03-11
申请号：US13596687
申请日：2012-08-28
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译： 在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。 一方面，制造FIN FET器件的方法包括以下步骤。 提供了在BOX上具有SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化多个翅片。 翅片上形成界面氧化物。 共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。 共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。 还提供了一种FIN FET器件。
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2.发明申请Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权金属栅极工作功能工程技术开启多阈值电压纳米线FET器件公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译： 制造纳米线FET器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 围绕每个纳米线形成界面氧化物。 共形栅电介质沉积在界面氧化物上。 保形第一栅极材料沉积在保形栅极电介质上。 工件功能设定材料沉积在保形第一栅极材料上。 第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。
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3.发明申请TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权门工功能工程技术降低平面CMOS器件中的短路通道效应公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译： 在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i） 存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。 存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。
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4.发明申请Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure 有权通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构公开(公告)号：US20130256797A1
公开(公告)日：2013-10-03
申请号：US13441048
申请日：2012-04-06
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译： 提供了非对称FET器件及其制造方法，其采用可变间距栅极。 一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个 有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。
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5.发明授权Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构公开(公告)号：US08822278B2
公开(公告)日：2014-09-02
申请号：US13434128
申请日：2012-03-29
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
摘要翻译： 提供了非对称FET器件及其制造方法，其采用可变间距栅极。 一方面，一种用于制造FET器件的方法包括以下步骤。 提供晶片。 使用STI在晶片中形成多个有效区域。 在晶片上形成多个栅极堆叠，其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少给定的一个有源区域，给定的源极侧的栅极到栅极间隔 有源面积大于给定有源区域的漏极侧上的栅极至栅极间距。 隔板形成在栅极堆叠的相对侧上。 在给定活动区域的源侧执行成角度的植入物。 还提供了FET器件。
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6.发明授权Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices 有权门功能工程技术可减少平面CMOS器件中的短沟道效应公开(公告)号：US08673731B2
公开(公告)日：2014-03-18
申请号：US13589707
申请日：2012-08-20
IPC分类号： H01L27/092
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.
摘要翻译： 提供了使用功能函数设置材料来减小平面CMOS器件中的短通道效应的门功能工程技术。 一方面，制造CMOS器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在其上具有沟槽的晶片上形成有图案的电介质，其中将形成栅叠层。 在每个沟槽中沉积：（i）共形栅极电介质（ii）共形栅极金属层和（iii）共形功函数设定金属层。 沉积到给定的一个沟槽中的保形栅极金属层的体积和/或共形功函设定金属层的体积与在给定沟槽中形成的栅极堆叠的长度成比例。 还提供了CMOS器件。
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7.发明授权Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices 有权金属栅极工作功能工程技术，可实现多个阈值电压纳米线FET器件公开(公告)号：US08658518B1
公开(公告)日：2014-02-25
申请号：US13588724
申请日：2012-08-17
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译： 制造纳米线FET器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 围绕每个纳米线形成界面氧化物。 共形栅电介质沉积在界面氧化物上。 保形第一栅极材料沉积在保形栅极电介质上。 工件功能设定材料沉积在保形第一栅极材料上。 第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。
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8.发明申请TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权门工功能工程技术降低平面CMOS器件中的短路通道效应公开(公告)号：US20140051225A1
公开(公告)日：2014-02-20
申请号：US13589707
申请日：2012-08-20
IPC分类号： H01L21/76
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.
摘要翻译： 提供了使用功能函数设置材料来减小平面CMOS器件中的短通道效应的门功能工程技术。 一方面，制造CMOS器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在其上具有沟槽的晶片上形成有图案的电介质，其中将形成栅叠层。 在每个沟槽中沉积：（i）共形栅极电介质（ii）共形栅极金属层和（iii）共形功函数设定金属层。 沉积到给定一个沟槽中的保形栅极金属层的体积和/或共形功函设定金属层的体积与在给定沟槽中形成的栅极堆叠的长度成比例。 还提供了CMOS器件。
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9.发明授权Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构公开(公告)号：US08823064B2
公开(公告)日：2014-09-02
申请号：US13441048
申请日：2012-04-06
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译： 提供了非对称FET器件及其制造方法，其采用可变间距栅极。 一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个 有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。
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10.发明授权Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices 有权金属栅极工作功能工程技术，可实现多个阈值电压纳米线FET器件公开(公告)号：US08659006B1
公开(公告)日：2014-02-25
申请号：US13597802
申请日：2012-08-29
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译： 纳米线FET器件包括在BOX上具有SOI层的SOI晶片和在SOI层中图案化的多个纳米线和焊盘，其中纳米线悬挂在BOX上; 围绕每个纳米线的界面氧化物; 以及围绕每个纳米线的至少一个栅极堆叠，所述栅极堆叠具有（i）界面氧化物上存在的共形栅极电介质（ii）共形栅极电介质上的共形第一栅极材料（iii）上的功函数设定材料 保形第一栅极材料，以及（iv）工作功能设定材料上的第二栅极材料。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。
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