公开(公告)号：US07561474B2

公开(公告)日：2009-07-14

申请号：US11965552

申请日：2007-12-27

申请人： Ju In Kim ,  Ju Yeab Lee

发明人： Ju In Kim ,  Ju Yeab Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage. During a second verify operation using the second verify voltage, a sensing current is adjusted by controlling voltages applied as a bit line select signal and an evaluation time period. Therefore, the threshold voltage of the memory cell can be measured higher or lower than its actual value and the width of a threshold voltage distribution is reduced.

摘要翻译： 使用第一和第二验证电压执行对战程序验证操作。 为了在增量步进脉冲程序实现期间减小阈值电压分布的宽度，使用第一验证电压和第二验证电压来验证相应的存储器单元的数据两次。 在使用第二验证电压的第二验证操作期间，通过控制作为位线选择信号和评估时间段施加的电压来调节感测电流。 因此，可以将存储单元的阈值电压测量为高于或低于其实际值，并且减小阈值电压分布的宽度。

公开(公告)号：US07796438B2

公开(公告)日：2010-09-14

申请号：US11951315

申请日：2007-12-05

申请人： Ju In Kim ,  Ju Yeab Lee

发明人： Ju In Kim ,  Ju Yeab Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3468 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3481

摘要： A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element enables the first latch during a verify operation of a first program based on a first verify voltage, and enables or disables the first latch in order to execute a verify operation of a second program based on a second verify voltage lower than the first verify voltage depending on whether data to be programmed has been stored in the second latch.

摘要翻译： 闪存器件可以包括存储单元阵列，页缓冲器单元和开关元件。 页面缓冲单元可以包括第一和第二锁存器，并且被配置为将数据编程到存储单元阵列中并从存储单元阵列读取数据。 基于第一验证电压，开关元件在第一程序的验证操作期间使第一锁存器能够启用或禁用第一锁存器，以便基于低于第一锁存器的第二验证电压执行第二程序的验证操作 根据要编程的数据是否存储在第二个锁存器中来验证电压。

公开(公告)号：US20090052240A1

公开(公告)日：2009-02-26

申请号：US11951315

申请日：2007-12-05

申请人： Ju In Kim ,  Ju Yeab Lee

发明人： Ju In Kim ,  Ju Yeab Lee

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C16/3468 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3481

摘要： A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element enables the first latch during a verify operation of a first program based on a first verify voltage, and enables or disables the first latch in order to execute a verify operation of a second program based on a second verify voltage lower than the first verify voltage depending on whether data to be programmed has been stored in the second latch.

摘要翻译： 闪存器件可以包括存储单元阵列，页缓冲器单元和开关元件。 页面缓冲单元可以包括第一和第二锁存器，并且被配置为将数据编程到存储单元阵列中并从存储单元阵列读取数据。 基于第一验证电压，开关元件在第一程序的验证操作期间使第一锁存器能够启用或禁用第一锁存器，以便基于低于第一锁存器的第二验证电压执行第二程序的验证操作 根据要编程的数据是否存储在第二个锁存器中来验证电压。

公开(公告)号：US20090003084A1

公开(公告)日：2009-01-01

申请号：US11965193

申请日：2007-12-27

申请人： Ju In Kim ,  Ju Yeab Lee

发明人： Ju In Kim ,  Ju Yeab Lee

IPC分类号： G11C16/14

CPC分类号： G11C16/0483 ,  G11C16/3454

摘要： In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit lines are precharged to a predetermined level, a ground voltage is applied to the word lines of all the memory cells in the block. The memory cells are evaluated for a predetermined time shorter than an evaluation time of a read operation. Whether or not a memory cell passing a verify operation exists among the memory cells is sensed. Resultantly, when the memory cell passing the verify operation exists, the memory cells in the block are programmed to a desired level using a predetermined program voltage and a step voltage.

摘要翻译： 在包括所选择的第一位线和未选择的第二位线的闪速存储器件的驱动方法中，将脉冲的编程电压施加到通过擦除验证操作的块中的所有存储器单元的字线。 在将第一和第二位线预充电至预定电平之后，将接地电压施加到块中所有存储单元的字线。 对存储单元进行评估比读操作的评估时间短的预定时间。 感测到存储单元之间是否存在通过验证操作的存储单元。 因此，当通过验证操作的存储单元存在时，使用预定的编程电压和阶跃电压将块中的存储单元编程到期望的电平。

公开(公告)号：US08279675B2

公开(公告)日：2012-10-02

申请号：US12621873

申请日：2009-11-19

申请人： Ju Yeab Lee ,  Keon Soo Shim

发明人： Ju Yeab Lee ,  Keon Soo Shim

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.

摘要翻译： 一种非易失性存储器件，包括：位线电压供给单元，被配置为提供电源电压，从第三参考电压减去第二参考电压的第二电压或者减去第一参考电压的第三电压 根据存储在第一锁存单元中的数据的第三参考电压，包括在页缓冲器中的第二锁存单元和第三锁存单元，以及位线电压设置单元，被配置为传送0V的电压或输出电压 根据存储在第一，第二和第三锁存单元中的数据，将位线电压供应单元的位线移动到位线。

公开(公告)号：US07193897B2

公开(公告)日：2007-03-20

申请号：US11182566

申请日：2005-07-15

申请人： Ju Yeab Lee

发明人： Ju Yeab Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/20 ,  G11C7/1021 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/18

摘要： Disclosed herein is a NAND flash memory device capable of changing a block size. In NAND flash memory devices capable of changing a block size, each memory block is divided into two page groups. Each memory block includes two block switches to select each page group in response to an external address signal. During an erasing operation, the block size is easily variable by applying an erasure voltage to one or two page groups.

摘要翻译： 本文公开了能够改变块大小的NAND闪存器件。 在能够改变块大小的NAND闪存器件中，每个存储块被分成两个页组。 每个存储块包括两个块开关，以响应于外部地址信号来选择每个页组。 在擦除操作期间，通过对一个或两个页组施加擦除电压，块大小容易变化。

公开(公告)号：US08351267B2

公开(公告)日：2013-01-08

申请号：US12827754

申请日：2010-06-30

申请人： Seung Hwan Baik ,  Ju Yeab Lee

发明人： Seung Hwan Baik ,  Ju Yeab Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628

摘要： A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：对第一存储器单元和第二存储器单元执行第一程序操作，使得第一和第二存储器单元的阈值电压具有低于第一目标电平的第一参考电平，第一存储器单元具有 所述第一目标级别作为第一目标级别，并且所述第二存储器单元具有比所述第一目标级别高的第二目标级别作为第二目标级别; 对所述第二存储器单元执行第二编程操作，使得所述第二存储器单元的阈值电压具有低于所述第二目标电平的第二参考电平; 以及对所述第一和第二存储器单元执行第三程序操作以具有各自的目标电平。

公开(公告)号：US08270221B2

公开(公告)日：2012-09-18

申请号：US12780192

申请日：2010-05-14

申请人： Ju Yeab Lee

发明人： Ju Yeab Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/06 ,  H01L27/11521

摘要： A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor, a latch unit, including a first latch for storing a detection result of a threshold voltage of a second memory cell adjacent to a first memory cell selected from among the memory cells and a second latch for storing a detection result of a threshold voltage of the first memory cell, and a first reset unit electrically coupled between the first and second latches and configured to reset the second latch, during a time in which a read operation is performed on the first memory cell, in response to a first reset signal and the detection result stored in the first latch.

摘要翻译： 非易失性存储器件包括一个单元串，包括耦合到位线的漏极选择晶体管，耦合到公共源极线的源极选择晶体管和串联耦合在漏极选择晶体管和源极选择晶体管之间的存储单元， 单元，包括用于存储与从所述存储单元中选择的第一存储单元相邻的第二存储单元的阈值电压的检测结果的第一锁存器和用于存储所述第一存储器单元的阈值电压的检测结果的第二锁存器 以及电耦合在第一和第二锁存器之间并且被配置为在对第一存储器单元执行读取操作的时间期间复位第二锁存器的第一复位单元，响应于第一复位信号和存储的检测结果 在第一个闩锁。

公开(公告)号：US07623385B2

公开(公告)日：2009-11-24

申请号：US11965191

申请日：2007-12-27

申请人： Nam Kyeong Kim ,  Ju Yeab Lee ,  Keum Hwan Noh

发明人： Nam Kyeong Kim ,  Ju Yeab Lee ,  Keum Hwan Noh

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/3427

摘要： Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.

摘要翻译： 提供了一种读取用于按下读取干扰的闪速存储器件的方法。 根据该方法，将第一电压施加到漏极选择晶体管的栅极以使漏极选择晶体管导通，并且将读取电压施加到多个存储单元中的选定晶体管的栅极。 然后，对多个存储单元中的未选择晶体管的栅极施加通过电压。 此外，当施加通过电压时，施加第一通过电压，然后在施加第一通过电压之后经过预定时间之后施加第二通过电压。 第二通过电压具有与第一通过电压不同的电平。

公开(公告)号：US07046554B2

公开(公告)日：2006-05-16

申请号：US11009749

申请日：2004-12-10

申请人： Ju Yeab Lee

发明人： Ju Yeab Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： Disclosed are a page buffer of a flash memory device and data program method using the same. After two data are sequentially stored in a main register (first latch) and a cache register (second latch) provided in a page buffer, they are respectively transferred to an even bit line and an odd bit line at the same time, and a bias needed for a program is applied to cells connected to the even bit line and the odd bit line, respectively, whereby the program is performed at the same time. Therefore, the number and time of operations for data loading, program operation and program verification can be reduced by half and the operating speed of the device can be improved.

摘要翻译： 公开了闪速存储器件的页面缓冲器和使用其的数据程序方法。 在将两个数据顺次存储在页缓冲器中提供的主寄存器（第一锁存器）和高速缓存寄存器（第二锁存器）中之后，它们分别被同时传送到偶位线和奇数位线，偏置 将节目所需的分别应用于连接到偶位线和奇数位线的单元，从而同时执行程序。 因此，可以将数据加载，程序操作和程序验证的操作次数和时间减少一半，并且可以提高设备的操作速度。