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公开(公告)号:US09812367B2
公开(公告)日:2017-11-07
申请号:US14621440
申请日:2015-02-13
申请人: Ju-Youn Kim , Ji-Hwan An , Kwang-Yul Lee , Tae-Won Ha , Jeong-Nam Han
发明人: Ju-Youn Kim , Ji-Hwan An , Kwang-Yul Lee , Tae-Won Ha , Jeong-Nam Han
IPC分类号: H01L21/8234 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/49 , H01L21/311 , H01L21/3213
CPC分类号: H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/31138 , H01L21/32139 , H01L21/823431 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.