公开(公告)号：US20070083839A1

公开(公告)日：2007-04-12

申请号：US11247630

申请日：2005-10-11

申请人： Juergen Lahner ,  Juergen Dirks ,  Balamurugan Balasubramanian

发明人： Juergen Lahner ,  Juergen Dirks ,  Balamurugan Balasubramanian

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5045

摘要： A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.

摘要翻译： 公开了一种开发电路设计的方法。 该方法通常包括以下步骤：（A）基于从设计者接收的多个编辑来编辑用于电路设计的文件，该文件包含用硬件描述语言编写的代码，（B）表征文件中的代码，同时 设计人员正在编辑代码以生成多个表征结果;（C）基于对于电路设计和表征结果的多个目标的比较，向设计者生成多个建议以修改代码。

公开(公告)号：US07082584B2

公开(公告)日：2006-07-25

申请号：US10427609

申请日：2003-04-30

申请人： Juergen Lahner ,  Kiran Atmakuri ,  Kavitha Chaturvedula ,  Balamurugan Balasubramanian ,  Krishna Devineni ,  Srinivas Adusumalli ,  Randall P. Fry ,  Gregory A. Pierce

发明人： Juergen Lahner ,  Kiran Atmakuri ,  Kavitha Chaturvedula ,  Balamurugan Balasubramanian ,  Krishna Devineni ,  Srinivas Adusumalli ,  Randall P. Fry ,  Gregory A. Pierce

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.

摘要翻译： 一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。 选择了一种集成电路设计供应商的设计规则的RTL平台。 设计规则从图形用户界面的RTL平台显示。 从图形用户界面中选择了多个设计规则。 在RTL代码的RTL平台中对每个选定的设计规则进行分析。 生成分析结果作为每个选定设计规则的输出。

公开(公告)号：US20070079273A1

公开(公告)日：2007-04-05

申请号：US11244530

申请日：2005-10-05

申请人： Juergen Lahner ,  Balamurugan Balasubramanian ,  Randall Fry

发明人： Juergen Lahner ,  Balamurugan Balasubramanian ,  Randall Fry

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A method of placing and routing an integrated circuit design includes steps of (a) generating an initial placement and routing for at least a portion of an integrated circuit design; (b) analyzing the initial placement and routing of the integrated circuit design to find a critical location; (c) partitioning the initial placement and routing of the integrated circuit design into a series of nested shells wherein each shell surrounds the critical location and each preceding shell; (d) selecting an ordering of the shells; (e) selecting at least one of a timing constraint and an area constraint for each shell; and (f) placing and routing each shell in the order selected in step (d) according to the at least one timing constraint and area constraint selected in step (e).

摘要翻译： 放置和布线集成电路设计的方法包括以下步骤：（a）为集成电路设计的至少一部分生成初始放置和布线; （b）分析集成电路设计的初始放置和路由以找到关键位置; （c）将集成电路设计的初始放置和布线划分成一系列嵌套的壳体，其中每个壳体围绕关键位置和每个先前的壳体; （d）选择炮弹的命令; （e）为每个壳体选择时序约束和面积约束中的至少一个; 以及（f）根据在步骤（e）中选择的至少一个定时约束和区域约束，以步骤（d）中选择的顺序放置和布置每个外壳。

公开(公告)号：US20070079266A1

公开(公告)日：2007-04-05

申请号：US11241033

申请日：2005-09-30

申请人： Krishna Devineni ,  Juergen Lahner ,  Gregory Pierce ,  Balamurugan Balasubramanian ,  Srinivas Adusumalli ,  Kiran Atmakuri ,  Kavitha Chaturvedula ,  Randall Fry

发明人： Krishna Devineni ,  Juergen Lahner ,  Gregory Pierce ,  Balamurugan Balasubramanian ,  Srinivas Adusumalli ,  Kiran Atmakuri ,  Kavitha Chaturvedula ,  Randall Fry

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.

摘要翻译： 一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。 在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的 集成电路设计中的每个设计规则违规的主要和次要对象列表。 每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略 违反设计关闭指引报告。

公开(公告)号：US06907588B2

公开(公告)日：2005-06-14

申请号：US10334743

申请日：2002-12-31

申请人： Balamurugan Balasubramanian ,  Juergen Lahner ,  Srinivas Adusumalli

发明人： Balamurugan Balasubramanian ,  Juergen Lahner ,  Srinivas Adusumalli

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.

摘要翻译： 估计寄存器传送级代码的拥塞的方法包括以下步骤：接收作为输入的从寄存器传送级代码映射的平面图，识别平面图中的区域，计算平面图中的区域的路由需求数，计算路由资源号 对于平面图中的区域，并且根据路由需求号码和路由资源号码生成寄存器传送级别代码的拥塞估计。

公开(公告)号：US06757885B1

公开(公告)日：2004-06-29

申请号：US10334570

申请日：2002-12-31

申请人： Srinivas Adusumalli ,  Juergen Lahner ,  Balamurugan Balasubramanian

发明人： Srinivas Adusumalli ,  Juergen Lahner ,  Balamurugan Balasubramanian

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.

摘要翻译： 一种生成用于寄存器传送级代码的长度矩阵的方法，包括用于接收作为输入寄存器传送级代码，I / O块列表，多个编译单元和用户定义的分层深度的步骤; 将所述寄存器传送级代码映射到设计库，生成所述多个编译单元的连接矩阵，从所述连接矩阵生成互连优先级列表，从所述互连优先级列表生成所述编译单元的布局坐标以及所述连接矩阵 并且产生作为连接矩阵和放置坐标中的至少一个的输出。

公开(公告)号：US06990651B2

公开(公告)日：2006-01-24

申请号：US10438530

申请日：2003-05-14

申请人： Balamurugan Balasubramanian ,  Juergen Lahner ,  Srinivas Adusumalli

发明人： Balamurugan Balasubramanian ,  Juergen Lahner ,  Srinivas Adusumalli

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.

摘要翻译： 集成电路设计库包括代表集成电路中的设计元件的定时参数; 表示集成电路中的设计元素的面积大小参数; 以及路线需求参数，其表示针对定时参数和面积大小参数的每个值的设计元素所需的连接数。

公开(公告)号：US07380228B2

公开(公告)日：2008-05-27

申请号：US10984115

申请日：2004-11-08

申请人： Randall P. Fry ,  Gregory Pierce ,  Juergen Lahner

发明人： Randall P. Fry ,  Gregory Pierce ,  Juergen Lahner

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.

摘要翻译： 一种用于将定时违规与关键结构相关联的集成电路设计的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的关键结构; 以及（c）生成用于静态时序分析工具的输出脚本，该工具包括对关键结构的输入端具有起始点的路径的定时检查以及临界结构输出端的终点。

公开(公告)号：US06546538B1

公开(公告)日：2003-04-08

申请号：US09523224

申请日：2000-03-10

申请人： Shalini Rubdi ,  Stefan Graef ,  Juergen Lahner

发明人： Shalini Rubdi ,  Stefan Graef ,  Juergen Lahner

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： Provided is an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. An area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device. Also provided is a technique for supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor. Then, one plate of the capacitor is connected to power, the other plate of the capacitor is connected to ground, and the plates of the capacitor are also connected to locations on the substrate of the IC device.

摘要翻译： 提供了一种集成电路（IC）装置，其包括其上形成有电子部件的半导体基板和布线有多个金属层。 在多个金属层上形成的电容器包括形成在第一金属层上的第一板和形成在与第一金属层相邻的第二金属层上的第二板。 第一板和第二板重叠的区域的宽度至少是IC器件上典型导线宽度的两倍。 还提供了一种用于向具有用于布线的多个金属层的集成电路（IC）装置和用于形成电子部件的基板的集成电路（IC）装置的位置供电和接地的技术。 最初，该技术识别彼此相邻的多个金属层中的两个具有开放空间的重叠区域。 然后在两个金属层中的每一个的重叠区域中形成一个板，以构成电容器。 然后，电容器的一个板连接到电源，电容器的另一个板连接到地，并且电容器的板也连接到IC器件的基板上的位置。

公开(公告)号：US07086015B2

公开(公告)日：2006-08-01

申请号：US10844664

申请日：2004-05-12

申请人： Juergen Lahner ,  Kiran Atkmakuri ,  Kavitha Chaturvedula

发明人： Juergen Lahner ,  Kiran Atkmakuri ,  Kavitha Chaturvedula

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

摘要翻译： 公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括以下步骤：（a）作为输入接收用于集成电路设计的第一寄存器传送级代码; （b）接收用户定义的最佳多路复用结构作为输入; （c）分析第一寄存器传送级代码以识别关键的多路复用结构; （d）将全局多路复用结构划分为与用户定义的最佳多路复用结构相同的本地多路复用结构; 以及（e）为所述集成电路设计产生用本地多路复用结构代替所述全局多路复用结构的第二寄存器传送级代码作为输出。