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公开(公告)号：US07813163B2
公开(公告)日：2010-10-12
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译： 提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时， 对于写入，选择了传递设备。 此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。 所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。
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公开(公告)号：US20090059688A1
公开(公告)日：2009-03-05
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译： 提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时， 对于写入，选择了传递设备。 此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。 所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。
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公开(公告)号：US20060179396A1
公开(公告)日：2006-08-10
申请号：US11350149
申请日：2006-02-08
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。
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4.发明授权Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit 失效提高SRAM单元，SRAM单元，SRAM阵列和写入电路性能的方法公开(公告)号：US07626851B2
公开(公告)日：2009-12-01
申请号：US11771014
申请日：2007-06-29
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.
摘要翻译： 描述了一种改善包括多个SRAM单元的SRAM单元或SRAM阵列性能的方法。 电池由第一高电压供电。 该单元可通过连接到写入电路的至少一个位线进行读取和写入操作。 该单元进一步可由至少一个字线寻址，以便通过位线访问该单元。 为了访问单元进行读或写操作，字线由第一较高电压提供，位线由第二较低电压提供。 在写操作期间，写电路由第一较高电压驱动，同时位线仍处于较低电压。 还描述了SRAM单元，SRAM阵列加上用于执行该方法的写入电路。
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5.发明申请Wordline Booster Design Structure and Method of Operating a Wordline Booster Circuit 有权Wordline Booster设计结构和操作字线加速电路的方法公开(公告)号：US20080068902A1
公开(公告)日：2008-03-20
申请号：US11847759
申请日：2007-08-30
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C8/08 , G11C11/413
摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.
摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。
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公开(公告)号：US20080256413A1
公开(公告)日：2008-10-16
申请号：US11868637
申请日：2007-10-08
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), Which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal, of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到相邻的邻近树（12）路径的次级输入（32）的信号组合 和/我们的前一个子树。
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7.发明授权Wordline booster design structure and method of operating a wordine booster circuit 有权Wordline助推器设计结构和操作字提升电路的方法公开(公告)号：US07921388B2
公开(公告)日：2011-04-05
申请号：US11847759
申请日：2007-08-30
CPC分类号： G11C5/145 , G11C8/08 , G11C11/413
摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.
摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。
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公开(公告)号：US07755408B2
公开(公告)日：2010-07-13
申请号：US11868637
申请日：2007-10-08
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /我们以前的子树。
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9.发明申请DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT 失效提高SRAM单元，SRAM单元，SRAM阵列和写入电路性能的设计结构公开(公告)号：US20090154263A1
公开(公告)日：2009-06-18
申请号：US11954672
申请日：2007-12-12
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.
摘要翻译： 描述体现在机器可读介质中以改善包括多个SRAM单元的SRAM单元或SRAM阵列的性能的设计结构。 该设计结构包括用于SRAM单元或SRAM阵列的写入电路。 写入电路包括用于开启和关闭写入电路的门。 电池由第一高电压供电。 该单元可通过连接到写入电路的至少一个位线进行读取和写入操作。 该单元进一步可由至少一个字线寻址，以便通过位线访问该单元。 为了访问单元进行读或写操作，字线由第一较高电压提供，位线由第二较低电压提供。 在写操作期间，写电路由第一较高电压驱动，同时位线仍处于较低电压。
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10.发明申请METHOD TO IMPROVE PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT 失效提高SRAM单元，SRAM单元，SRAM阵列和写入电路性能的方法公开(公告)号：US20080123442A1
公开(公告)日：2008-05-29
申请号：US11771014
申请日：2007-06-29
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.
摘要翻译： 描述了一种改善包括多个SRAM单元的SRAM单元或SRAM阵列性能的方法。 电池由第一高电压供电。 该单元可通过连接到写入电路的至少一个位线进行读取和写入操作。 该单元进一步可由至少一个字线寻址，以便通过位线访问该单元。 为了访问单元进行读或写操作，字线由第一较高电压提供，位线由第二较低电压提供。 在写操作期间，写电路由第一较高电压驱动，同时位线仍处于较低电压。 还描述了SRAM单元，SRAM阵列加上用于执行该方法的写入电路。
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