公开(公告)号：US06590799B1

公开(公告)日：2003-07-08

申请号：US10158279

申请日：2002-05-29

申请人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

发明人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

IPC分类号： G11C1122

CPC分类号： G11C29/028 ,  G11C11/22 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/2602 ,  G11C2029/5002

摘要： A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

摘要翻译： 用于测量从FeRAM单元读出的电荷分布的方法和电路足够快以进行片上缺陷检测和参数调整。 比较器型读出放大器和参考电压发生器使用来自FeRAM单元的一次读出电荷测量位线电荷或电压，并将所得位线电压与一系列参考电压进行比较。 来自读出放大器的一系列结果信号指示位线电压何时近似等于参考电压。 结果信号可以输出用于分析和/或内部使用，用于缺陷检测或设置操作参数，例如在读取操作期间使用的参考。

公开(公告)号：US06735106B2

公开(公告)日：2004-05-11

申请号：US10190102

申请日：2002-07-02

申请人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

发明人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

IPC分类号： G11C1122

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

摘要翻译： 诸如FeRAM的存储器实现加速疲劳操作，其同时改变大量存储器单元的存储状态并且可以快速重复。 在一个实施例中，FeRAM包括多个段，每个段中的板线与其它段中的板线隔离。 第一次疲劳操作使用字线的标准读/写解码，但同时激活所有段。 第二次疲劳操作激活所有的段和所有的板条，并在每个板组组中锻炼一行记忆单元。 第三个疲劳操作类似于第二个但是在板组组中的行循环，使得第三疲劳操作的重复次数对于每个FeRAM单元同样疲劳。

公开(公告)号：US06952623B2

公开(公告)日：2005-10-04

申请号：US10190408

申请日：2002-07-02

申请人： Hugh P. McAdams ,  James W. Grace ,  Ralph H. Lanham

发明人： Hugh P. McAdams ,  James W. Grace ,  Ralph H. Lanham

IPC分类号： G01R31/28 ,  G06K17/00 ,  G06K19/07 ,  G11C11/22 ,  G11C16/20 ,  G11C29/12 ,  G11C29/44 ,  H01L21/66 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  G06F19/00

CPC分类号： G11C29/44 ,  G06K2017/0045 ,  G11C11/22 ,  G11C16/20 ,  G11C2029/4402

摘要： An integrated circuit (IC) chip contains a small non-volatile “ID” memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.

摘要翻译： 集成电路（IC）芯片包含小型非易失性“ID”存储器，例如存储与IC芯片的制造，测试和性能相关的信息的FeRAM阵列。 存储的信息可以包括但不限于序列号，晶片ID，批次ID，日期代码，芯片历史，测试数据和性能信息。 芯片上的存储信息消除了将信息与IC芯片匹配的任何困难，并提供制造商可能发现有用的任何信息的灵活的永久记录。 因此，ID存储器允许IC的跟踪和识别达到以前不可行的程度。 此外，自检可以将存储在ID存储器中的先前测试结果与当前的自检结果进行比较，以检测缺陷或选择集成电路的工作参数。

公开(公告)号：US5130989A

公开(公告)日：1992-07-14

申请号：US494016

申请日：1990-03-15

申请人： Daryl E. Anderson ,  Ralph H. Lanham ,  Neal C. Jaarsma

发明人： Daryl E. Anderson ,  Ralph H. Lanham ,  Neal C. Jaarsma

IPC分类号： G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/56

CPC分类号： G01R31/318516

摘要： A method for testing a systolic array in which a plurality of sequential registers is each connected to the rest by an intervening logic component. Each register includes a plurality of memory elements. Each register can be enabled to act as a latch register whereby digital data is loaded into an output therefrom in parallel or as a shift register whereby digital data is shifted sequentially in each register from one memory element to the next adjacent memory element. A test vector consisting of a preselected string of digital data is shifted in parallel into each of the registers. The test vector in each register is loaded into the associated logic component which operates on the vector and stores the data in the next adjacent register. The resulting data is serially clocked from each register onto unique bus nodes and examined in parallel to determine whether or not the expected result was obtained.

摘要翻译： 一种用于测试心脏阵列的方法，其中多个顺序寄存器各自通过中间的逻辑组件连接到其余的。 每个寄存器包括多个存储元件。 每个寄存器可以被用作锁存寄存器，由此数字数据被并行地加载到其输出中，或者作为移位寄存器，由此数字数据在每个寄存器中从一个存储元件顺序地移位到下一个相邻的存储元件。 由预选的数字数据串组成的测试向量并行移位到每个寄存器中。 每个寄存器中的测试向量被加载到相关联的逻辑组件中，该组件对向量进行操作并将数据存储在下一个相邻寄存器中。 所得到的数据从每个寄存器被串行计时到独特的总线节点上并行检查以确定是否获得预期的结果。

公开(公告)号：US06724645B1

公开(公告)日：2004-04-20

申请号：US10356443

申请日：2003-01-30

申请人： Ralph H. Lanham ,  David Victor Pietromonaco

发明人： Ralph H. Lanham ,  David Victor Pietromonaco

IPC分类号： G11C700

CPC分类号： G11C11/22

摘要： An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and delayed to the subsequent clock cycle. A FeRAM memory cell having two ports is needed so that consecutive operations do not conflict with each other. A read operation is initiated through a first port in a first clock cycle. In the subsequent clock cycle, the rewrite finishes through the first port. The next operation utilizes the second port, without conflicting with the rewrite process. By alternating ports used in each clock cycle, the rewrite step is hidden in the subsequent clock cycle to shorten the read operation. In an alternate method, all read operations are initiated through one port, while the second port is reserved exclusively for write operations and rewrites.

摘要翻译： 公开了一种用于缩短破坏性读取存储器中的读取操作（通常是最长操作）的装置和方法。 重写步骤与读取操作分离并延迟到随后的时钟周期。 需要具有两个端口的FeRAM存储单元，使得连续的操作彼此不冲突。 在第一个时钟周期内通过第一个端口启动读取操作。 在随后的时钟周期中，重写通过第一个端口完成。 下一个操作使用第二个端口，而不会与重写过程冲突。 通过在每个时钟周期中交替使用端口，重写步骤在随后的时钟周期中被隐藏，以缩短读取操作。 在另一种方法中，所有读取操作都是通过一个端口启动的，而第二个端口专用于写操作和重写。